{"product_id":"phase-locked-loops-isbn-9781119909040","title":"Phase-Locked Loops","description":"\u003cb\u003ePhase-Locked Loops\u003c\/b\u003e \u003cp\u003e\u003cb\u003eDiscover the essential materials for phase-locked loop circuit design, from fundamentals to practical design aspects\u003c\/b\u003e \u003c\/p\u003e\u003cp\u003eA phase-locked loop (PLL) is a type of circuit with a range of important applications in telecommunications and computing. It generates an output signal with a controlled relationship to an input signal, such as an oscillator which matches the phases of input and output signals. This is a critical function in coherent communication systems, with the result that the theory and design of these circuits are essential to electronic communications of all kinds. \u003c\/p\u003e\u003cp\u003e\u003ci\u003ePhase-Locked Loops: System Perspectives and Circuit Design Aspects\u003c\/i\u003e provides a concise, accessible introduction to PLL design. It introduces readers to the role of PLLs in modern communication systems, the fundamental techniques of phase-lock circuitry, and the possible applications of PLLs in a wide variety of electronic communications contexts. The first book of its kind to incorporate modern architectures and to balance theoretical fundamentals with detailed design insights, this promises to be a must-own text for students and industry professionals. \u003c\/p\u003e\u003cp\u003eThe book also features: \u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eCoverage of PLL basics with insightful analysis and examples tailored for circuit designers\u003c\/li\u003e \u003cli\u003eApplications of PLLs for both wireless and wireline systems\u003c\/li\u003e \u003cli\u003ePractical circuit design aspects for modern frequency generation, frequency modulation, and clock recovery systems\u003c\/li\u003e\n\u003c\/ul\u003e \u003cp\u003e\u003ci\u003ePhase-Locked Loops\u003c\/i\u003e is essential for graduate students and advanced undergraduates in integrated circuit design, as well researchers and engineers in electrical and computing subjects. \u003c\/p\u003e\u003cp\u003ePreface xiii\u003c\/p\u003e \u003cp\u003eAbout Authors xv\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Phase-Lock Technique 1\u003c\/p\u003e \u003cp\u003e1.2 Key Properties and Applications 2\u003c\/p\u003e \u003cp\u003e1.3 Organization and Scope of the Book 6\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart I Phase-Lock Basics 9\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Linear Model and Loop Dynamics 11\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Linear Model of the PLL 11\u003c\/p\u003e \u003cp\u003e2.2 Feedback System 13\u003c\/p\u003e \u003cp\u003e2.3 Loop Dynamics of the PLL 16\u003c\/p\u003e \u003cp\u003e2.4 Noise Transfer Function 26\u003c\/p\u003e \u003cp\u003e2.5 Charge-Pump PLL 29\u003c\/p\u003e \u003cp\u003e2.6 Other Design Considerations 39\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Transient Response 43\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Linear Transient Performance 44\u003c\/p\u003e \u003cp\u003e3.2 Nonlinear Transient Performance 52\u003c\/p\u003e \u003cp\u003e3.3 Practical Design Aspects 56\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart II System Perspectives 67\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Frequency and Spectral Purity 69\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Spur Generation and Modulation 69\u003c\/p\u003e \u003cp\u003e4.2 Phase Noise and Random Jitter 87\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Application Aspects 101\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Frequency Synthesis 102\u003c\/p\u003e \u003cp\u003e5.2 Clock-and-Data Recovery 112\u003c\/p\u003e \u003cp\u003e5.3 Clock Generation 120\u003c\/p\u003e \u003cp\u003e5.4 Synchronization 127\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart III Building Circuits 135\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 PhaseDetector 137\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Non-Memory Phase Detectors 137\u003c\/p\u003e \u003cp\u003e6.2 Phase-Frequency Detector 142\u003c\/p\u003e \u003cp\u003e6.3 Charge Pump 149\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Voltage-Controlled Oscillator 165\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Oscillator Basics 166\u003c\/p\u003e \u003cp\u003e7.2 LC VCO 175\u003c\/p\u003e \u003cp\u003e7.3 RING VCO 190\u003c\/p\u003e \u003cp\u003e7.4 Relaxation VCO 201\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 FrequencyDivider 209\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Basic Operation 209\u003c\/p\u003e \u003cp\u003e8.2 Circuit Design Considerations 219\u003c\/p\u003e \u003cp\u003e8.3 Other Topologies 229\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart IV PLL Architectures 237\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Fractional-N PLL 239\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Fractional-N Frequency Synthesis 239\u003c\/p\u003e \u003cp\u003e9.2 Frequency Synthesis with Delta-Sigma Modulation 249\u003c\/p\u003e \u003cp\u003e9.3 Quantization Noise Reduction Methods 271\u003c\/p\u003e \u003cp\u003e9.4 Frequency Modulation by Fractional-N PLL 278\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Digital-Intensive PLL 287\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 DPLL with Linear TDC 288\u003c\/p\u003e \u003cp\u003e10.2 DPLL with 1-Bit TDC 304\u003c\/p\u003e \u003cp\u003e10.3 Hybrid PLL 315\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Clock-and-Data Recovery PLL 325\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Loop Dynamics Considerations for CDR 325\u003c\/p\u003e \u003cp\u003e11.2 CDR PLL Architectures Based on Phase Detection 329\u003c\/p\u003e \u003cp\u003e11.3 Frequency Acquisition 340\u003c\/p\u003e \u003cp\u003e11.4 DLL-assisted CDR Architectures 344\u003c\/p\u003e \u003cp\u003e11.5 Open-Loop CDR Architectures 351\u003c\/p\u003e \u003cp\u003eReferences 355\u003c\/p\u003e \u003cp\u003eIndex 359\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eWoogeun Rhee, PhD,\u003c\/b\u003e is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He has over 25 years of professional career experience in integrated circuit design with nearly 10 years in industry and 16 years in academia. Dr. Rhee is one of a few researchers who made significant contributions to PLL architectures and circuits not only within different careers (academia and industry) but also over different fields (wireless and wireline systems). He is an IEEE Fellow. \u003c\/p\u003e\u003cp\u003e\u003cb\u003eZhiping Yu, PhD,\u003c\/b\u003e is a Professor at the School of Integrated Circuits, Tsinghua University, Beijing. He is an IEEE Life Fellow with over 400 published papers on subjects related to ICCAD, nanoelectronics and RF circuit design.   \u003c\/p\u003e\u003cp\u003e\u003cb\u003eDiscover the essential materials for phase-locked loop circuit design, from fundamentals to practical design aspects\u003c\/b\u003e \u003c\/p\u003e\u003cp\u003eA phase-locked loop (PLL) is a type of circuit with a range of important applications in telecommunications and computing. It generates an output signal with a controlled relationship to an input signal, such as an oscillator which matches the phases of input and output signals. This is a critical function in coherent communication systems, with the result that the theory and design of these circuits are essential to electronic communications of all kinds. \u003c\/p\u003e\u003cp\u003e\u003ci\u003ePhase-Locked Loops: System Perspectives and Circuit Design Aspects\u003c\/i\u003e provides a concise, accessible introduction to PLL design. It introduces readers to the role of PLLs in modern communication systems, the fundamental techniques of phase-lock circuitry, and the possible applications of PLLs in a wide variety of electronic communications contexts. The first book of its kind to incorporate modern architectures and to balance theoretical fundamentals with detailed design insights, this promises to be a must-own text for students and industry professionals. \u003c\/p\u003e\u003cp\u003eThe book also features: \u003c\/p\u003e\u003cul\u003e\n\u003cli\u003eCoverage of PLL basics with insightful analysis and examples tailored for circuit designers\u003c\/li\u003e \u003cli\u003eApplications of PLLs for both wireless and wireline systems\u003c\/li\u003e \u003cli\u003ePractical circuit design aspects for modern frequency generation, frequency modulation, and clock recovery systems\u003c\/li\u003e\n\u003c\/ul\u003e \u003cp\u003e\u003ci\u003ePhase-Locked Loops\u003c\/i\u003e is essential for graduate students and advanced undergraduates in integrated circuit design, as well researchers and engineers in electrical and computing subjects.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989774188773,"sku":"NP9781119909040","price":140.0,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781119909040.jpg?v=1761785427","url":"https:\/\/k12savings.com\/products\/phase-locked-loops-isbn-9781119909040","provider":"K12savings","version":"1.0","type":"link"}