{"product_id":"frequency-acquisition-techniques-for-phase-locked-loops-isbn-9781118168103","title":"Frequency Acquisition Techniques for Phase Locked Loops","description":"\u003cp\u003e\u003cb\u003eHow to acquire the input frequency from an unlocked state\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA phase locked loop (PLL) by itself cannot become useful until it has acquired the applied signal's frequency. Often, a PLL will never reach frequency acquisition (capture) without explicit assistive circuits. Curiously, few books on PLLs treat the topic of frequency acquisition in any depth or detail. \u003ci\u003eFrequency Acquisition Techniques for Phase Locked Loops\u003c\/i\u003e offers a no-nonsense treatment that is equally useful for engineers, technicians, and managers.\u003c\/p\u003e \u003cp\u003eSince mathematical rigor for its own sake can degenerate into intellectual \"rigor mortis,\" the author introduces readers to the basics and delivers useful information with clear language and minimal mathematics. With most of the approaches having been developed through years of experience, this completely practical guide explores methods for achieving the locked state in a variety of conditions as it examines:\u003c\/p\u003e \u003cul\u003e \u003cli\u003ePerformance limitations of phase\/frequency detector–based phase locked loops\u003c\/li\u003e \u003cli\u003eThe quadricorrelator method for both continuous and sampled modes\u003c\/li\u003e \u003cli\u003eSawtooth ramp-and-sample phase detector and how its waveform contains frequency error information that can be extracted\u003c\/li\u003e \u003cli\u003eThe benefits of a self-sweeping, self-extinguishing topology\u003c\/li\u003e \u003cli\u003eSweep methods using quadrature mixer-based lock detection\u003c\/li\u003e \u003cli\u003eThe use of digital implementations versus analog\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eFrequency Acquisition Techniques for Phase Locked Loops\u003c\/i\u003e is an important resource for RF\/microwave engineers, in particular, circuit designers; practicing electronics engineers involved in frequency synthesis, phase locked loops, carrier or clock recovery loops, radio-frequency integrated circuit design, and aerospace electronics; and managers wanting to understand the technology of phase locked loops and frequency acquisition assistance techniques or jitter attenuating loops.\u003cbr\u003e Errata can be found by visiting the Book Support Site at: \u003ca href=\"http:\/\/booksupport.wiley.com\/\"\u003ehttp:\/\/booksupport.wiley.com\u003c\/a\u003e\u003c\/p\u003e \u003cp\u003ePreface xi\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 A Review of PLL Fundamentals 3\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 What is a PLL?, 3\u003c\/p\u003e \u003cp\u003e2.2 Second-Order PLL, 7\u003c\/p\u003e \u003cp\u003e2.3 Second-Order PLL Type One, 7\u003c\/p\u003e \u003cp\u003e2.4 Second-Order PLL Type Two, 7\u003c\/p\u003e \u003cp\u003e2.5 Higher-Order PLL’s, 8\u003c\/p\u003e \u003cp\u003e2.6 Disturbances, 8\u003c\/p\u003e \u003cp\u003e2.7 Frequency Steering and Capture, 9\u003c\/p\u003e \u003cp\u003e2.8 Effect of DC Offsets or Noise Prior to the Loop Filter, 10\u003c\/p\u003e \u003cp\u003e2.9 Injection-Locked Oscillations, 15\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Simulating the PLL Linear Operation Mode 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Linear Model, 17\u003c\/p\u003e \u003cp\u003e3.2 A Word About Damping, 19\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Sideband Suppression Filtering 21\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Reference Sidebands and VCO Pushing, 21\u003c\/p\u003e \u003cp\u003e4.2 Superiority of the Cauer (or Elliptical) Filter, 22\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Pros and Cons of Sampled Data Phase Detection 25\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 What are the Forms of Sampled Data Phase Detectors?, 25\u003c\/p\u003e \u003cp\u003e5.2 A. Ramp and Sample Analog Phase Detector, 25\u003c\/p\u003e \u003cp\u003e5.3 B. The RF Sampling Phase Detector, 28\u003c\/p\u003e \u003cp\u003e5.4 C. Edge-Triggered S-R Flip-Flop, 29\u003c\/p\u003e \u003cp\u003e5.5 D. Edge-Triggered Flip-Flop Ensemble, 31\u003c\/p\u003e \u003cp\u003e5.6 E. Sample and Hold as a Phase Detector, 31\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Phase Compression 33\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Hard Limiting of a Signal Plus Noise 35\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Phase Noise and Other Spurious Interferers 39\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 The Mechanism for Phase Noise in an Oscillator, 42\u003c\/p\u003e \u003cp\u003e8.2 Additive Noise in an FM Channel and the Bowtie, 42\u003c\/p\u003e \u003cp\u003e8.3 Importance of FM Theory to Frequency Acquisition, 45\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Impulse Modulation and Noise Aliasing 47\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Impulse Train Spectrum, 47\u003c\/p\u003e \u003cp\u003e9.2 Sampling Phase Detector Noise, 47\u003c\/p\u003e \u003cp\u003e9.3 Spur Aliasing, 50\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Time and Phase Jitter, Heterodyning, and Multiplication 53\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Heterodyning and Resulting Time Jitter, 53\u003c\/p\u003e \u003cp\u003e10.2 Frequency Multiplication and Angle Modulation Index, 54\u003c\/p\u003e \u003cp\u003e10.3 Frequency Multiplication’s Role in Carrier Recovery, 54\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Carrier Recovery Applications and Acquisition 57\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Frequency Multiplier Carrier Recovery in General, 57\u003c\/p\u003e \u003cp\u003e11.2 The Simplest Form of Costas PLL, 59\u003c\/p\u003e \u003cp\u003e11.3 Higher Level Quadrature Demodulation Costas PLL, 61\u003c\/p\u003e \u003cp\u003e11.4 False Lock in BPSK Costas PLL, 62\u003c\/p\u003e \u003cp\u003e11.5 Additional Measures for Prevention of False Locking, 65\u003c\/p\u003e \u003cp\u003e11.6 False Lock Prevention Using DC Offset, 72\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Notes on Sweep Methods 73\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Sweep Waveform Superimposed Directly on VCO Input, 73\u003c\/p\u003e \u003cp\u003e12.2 Maximum Sweep Rate (Acceleration), 74\u003c\/p\u003e \u003cp\u003e12.3 False Lock due to High-Order Filtering, 77\u003c\/p\u003e \u003cp\u003e12.4 Sweep Waveform Applied Directly to PLL Loop Integrator, 79\u003c\/p\u003e \u003cp\u003e12.5 Self-Sweeping PLL, 79\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Nonsweep Acquisition Methods 85\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Delay Line Frequency Discriminator, 85\u003c\/p\u003e \u003cp\u003e13.2 The Fully Unbalanced Quadricorrelator, 87\u003c\/p\u003e \u003cp\u003e13.3 The Fully Balanced Quadricorrelator, 88\u003c\/p\u003e \u003cp\u003e13.4 The Multipulse Balanced Quadricorrelator, 89\u003c\/p\u003e \u003cp\u003e13.5 Conclusion Regarding Pulsed Frequency Detection, 91\u003c\/p\u003e \u003cp\u003e13.6 Quadricorrelator Linearity, 92\u003c\/p\u003e \u003cp\u003e13.7 Limiter Asymmetry due to DC Offset, 97\u003c\/p\u003e \u003cp\u003e13.8 Taylor Series Demonstrates Second-Order-Caused DC Offset, 100\u003c\/p\u003e \u003cp\u003e13.9 Third-Order Intermodulation Distortion and Taylor Series, 101\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 AM Rejection in Frequency Detection Schemes 105\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14.1 AM Rejection with Limiter and Interferer, 105\u003c\/p\u003e \u003cp\u003e14.2 AM Rejection of the Balanced Limiter\/Quadricorrelator Versus the Limiter\/Discriminator in the Presence of a Single Spur, 106\u003c\/p\u003e \u003cp\u003e14.3 Impairment due to Filter Response Tilt (Asymmetry), 110\u003c\/p\u003e \u003cp\u003e14.4 Bandpass Filter Geometric and Arithmetic Symmetry, 114\u003c\/p\u003e \u003cp\u003e14.5 Comments on Degree of Scrutiny, 117\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Interfacing the Frequency Discriminator to the PLL 119\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e15.1 Continuous Connection: Pros and Cons, 119\u003c\/p\u003e \u003cp\u003e15.2 Connection to PLL via a Dead Band, 120\u003c\/p\u003e \u003cp\u003e15.3 Switched Connection, 121\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 Actual Frequency Discriminator Implementations 125\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e16.1 Quadricorrelator, Low-Frequency Implementation, 125\u003c\/p\u003e \u003cp\u003e16.2 Frequency Ratio Calculating Circuit for Wide-Bandwidth Use, 128\u003c\/p\u003e \u003cp\u003e16.3 Dividing the Frequency and Resultant Implementation, 131\u003c\/p\u003e \u003cp\u003e16.4 Marriage of Both Frequency and Phaselock Loops, 135\u003c\/p\u003e \u003cp\u003e16.5 Comments on Spurs’ Numerical Influence on the VCO, 141\u003c\/p\u003e \u003cp\u003e16.6 Frequency Compression, 143\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 Clock Recovery Using a PLL 145\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e17.1 PLL Only, 145\u003c\/p\u003e \u003cp\u003e17.2 PLL with Sideband Crystal Filter(s), 152\u003c\/p\u003e \u003cp\u003e17.3 PLL with Sideband Cavity Filter, 153\u003c\/p\u003e \u003cp\u003e17.4 The Hogge Phase Detector, 161\u003c\/p\u003e \u003cp\u003e17.5 Bang–Bang Phase Detectors, 162\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 Frequency Synthesis Applications 165\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18.1 Direct Frequency Synthesis with Wadley Loop, 166\u003c\/p\u003e \u003cp\u003e18.2 Indirect Frequency Synthesis with PLLs, 173\u003c\/p\u003e \u003cp\u003e18.3 Simple Frequency Acquisition Improvement for a PLL, 175\u003c\/p\u003e \u003cp\u003e18.4 Hybrid Frequency Synthesis with DDS and PLL, 176\u003c\/p\u003e \u003cp\u003e18.5 Phase Noise Considerations, 181\u003c\/p\u003e \u003cp\u003e18.6 Pros and Cons of DDS-Augmented Synthesis, 185\u003c\/p\u003e \u003cp\u003e18.7 Multiple Loops, 185\u003c\/p\u003e \u003cp\u003e18.8 Reference Signal Considerations and Filtering, 186\u003c\/p\u003e \u003cp\u003e18.9 SNR of Various Phase Detectors, 187\u003c\/p\u003e \u003cp\u003e18.10 Phase Detector Dead Band (Dead Zone) and Remediation, 187\u003c\/p\u003e \u003cp\u003e18.11 Sideband Energy due to DC Offset Following Phase Detector, 191\u003c\/p\u003e \u003cp\u003e18.12 Brute Force PLL Frequency Acquisition via Speedup, 193\u003c\/p\u003e \u003cp\u003e18.13 Short-Term and Long-Term Settling, 193\u003c\/p\u003e \u003cp\u003e18.14 N-over-M Synthesis, 193\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 Injection Pulling of Multiple VCO’s as in a Serdes 195\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e19.1 Allowable Coupling Between any Two VCOs Versus Q and BW, 195\u003c\/p\u003e \u003cp\u003e19.2 Topology Suggestion for Eliminating the Injection Pulling, 195\u003c\/p\u003e \u003cp\u003e20 Digital PLL Example 199\u003c\/p\u003e \u003cp\u003e21 Conclusion 203\u003c\/p\u003e \u003cp\u003eReferences 205\u003c\/p\u003e \u003cp\u003eIndex 209\u003c\/p\u003e  \u003cp\u003e“Frequency Acquisition Techniques for Phase Locked Loops is an good resource for RF\/microwave engineers, in particular, circuit designers; practicing electronics engineers involved in frequency synthesis, phase locked loops, carrier or clock recovery loops, radio-frequency integrated circuit design, and aerospace electronics; and managers wanting to understand the technology of phase locked loops and frequency acquisition assistance techniques or jitter attenuating loops.”  (\u003ci\u003eMicrowave Journal\u003c\/i\u003e, 1 April 2013)\u003c\/p\u003e \u003cp\u003e\u003cb\u003eDANIEL B. TALBOT\u003c\/b\u003e currently runs a product development business specializing in RF\/analog engineering. He has years of industry experience as a chief technical engineer at DBX Corporation, LTX Corporation, and a principal or research engineer or equivalent at Raytheon, RCA David Sarnoff Labs, General Instrument, and several other aerospace and commercial electronics firms; has been granted eight U.S. patents in the field of RF\/analog\/fiber optic engineering; and is an elected Fellow of the Audio Engineering Society and a Life Member of the IEEE.\u003c\/p\u003e   \u003cp\u003e\u003cb\u003eHow to acquire the input frequency from an unlocked state\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA phase locked loop (PLL) by itself cannot become useful until it has acquired the applied signal's frequency. Often, a PLL will never reach frequency acquisition (capture) without explicit assistive circuits. Curiously, few books on PLLs treat the topic of frequency acquisition in any depth or detail. \u003ci\u003eFrequency Acquisition Techniques for Phase Locked Loops\u003c\/i\u003e offers a no-nonsense treatment that is equally useful for engineers, technicians, and managers.\u003c\/p\u003e \u003cp\u003eSince mathematical rigor for its own sake can degenerate into intellectual \"rigor mortis,\" the author introduces readers to the basics and delivers useful information with clear language and minimal mathematics. With most of the approaches having been developed through years of experience, this completely practical guide explores methods for achieving the locked state in a variety of conditions as it examines:\u003c\/p\u003e \u003cul\u003e \u003cli\u003ePerformance limitations of phase\/frequency detector–based phase locked loops\u003c\/li\u003e \u003cli\u003eThe quadricorrelator method for both continuous and sampled modes\u003c\/li\u003e \u003cli\u003eSawtooth ramp-and-sample phase detector and how its waveform contains frequency error information that can be extracted\u003c\/li\u003e \u003cli\u003eThe benefits of a self-sweeping, self-extinguishing topology\u003c\/li\u003e \u003cli\u003eSweep methods using quadrature mixer-based lock detection\u003c\/li\u003e \u003cli\u003eThe use of digital implementations versus analog\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eFrequency Acquisition Techniques for Phase Locked Loops\u003c\/i\u003e is an important resource for RF\/microwave engineers, in particular, circuit designers; practicing electronics engineers involved in frequency synthesis, phase locked loops, carrier or clock recovery loops, radio-frequency integrated circuit design, and aerospace electronics; and managers wanting to understand the technology of phase locked loops and frequency acquisition assistance techniques or jitter attenuating loops.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989245018341,"sku":"NP9781118168103","price":147.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781118168103.jpg?v=1761783357","url":"https:\/\/k12savings.com\/products\/frequency-acquisition-techniques-for-phase-locked-loops-isbn-9781118168103","provider":"K12savings","version":"1.0","type":"link"}