{"product_id":"esd-in-silicon-integrated-circuits-isbn-9780471498711","title":"ESD in Silicon Integrated Circuits","description":"* Examines the various methods available for circuit protection, including coverage of the newly developed ESD circuit protection schemes for VLSI circuits.\u003cbr\u003e * Provides guidance on the implementation of circuit protection measures.\u003cbr\u003e * Includes new sections on ESD design rules, layout approaches, package effects, and circuit concepts.\u003cbr\u003e * Reviews the new Charged Device Model (CDM) test method and evaluates design requirements necessary for circuit protection.Thema dieses Buches sind elektrostatische Entladungseffekte (ESD) in integrierten Siliciumschaltkreisen, die sich zu einem wesentlichen Problem der modernen hochintegrierten Schaltungen mit Strukturbreiten in Sub-Mikrometer-Dimensionen entwickelt haben. Diese 2. Auflage des klassischen Handbuchs liefert einen kompletten Überblick über alle Aspekte des ESD und die unmittelbaren Folgerungen für Entwurf und Entwicklung neuer Schaltkreise und Technologien. Die Hälfte des Materials wurde neu aufgenommen. das Autorenteam wurde um drei international anerkannte Experten erweitert. Preface\u003cbr\u003e \u003cbr\u003e 1. Introduction\u003cbr\u003e \u003cbr\u003e Background\u003cbr\u003e \u003cbr\u003e The ESD Problem\u003cbr\u003e \u003cbr\u003e Protecting against ESD\u003cbr\u003e \u003cbr\u003e Outline of the Book\u003cbr\u003e \u003cbr\u003e 2. ESD Phenomenon\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Electrostatic Voltage\u003cbr\u003e \u003cbr\u003e Discharge\u003cbr\u003e \u003cbr\u003e ESD Stress Models\u003cbr\u003e \u003cbr\u003e 3. Test Methods\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Human Body Model (HBM)\u003cbr\u003e \u003cbr\u003e Machine Model (MM)\u003cbr\u003e \u003cbr\u003e Charged Device Model (CDM)\u003cbr\u003e \u003cbr\u003e Socket Device Model (SDM)\u003cbr\u003e \u003cbr\u003e Metrology, Calibration, Verification\u003cbr\u003e \u003cbr\u003e Transmission Line Pulsing (TLP)\u003cbr\u003e \u003cbr\u003e Failure Criteria\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 4 Physics and Operation of ESD Protection Circuits\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Resistors\u003cbr\u003e \u003cbr\u003e Diodes\u003cbr\u003e \u003cbr\u003e Transistor Operation\u003cbr\u003e \u003cbr\u003e Transistor Operation Under ESD Conditions\u003cbr\u003e \u003cbr\u003e Electrothermal Effects\u003cbr\u003e \u003cbr\u003e SCR Operation\u003cbr\u003e \u003cbr\u003e Conclusion\u003cbr\u003e \u003cbr\u003e 5 ESD Protection Design Concepts and Strategy\u003cbr\u003e \u003cbr\u003e The Qualities of Good ESD Protection\u003cbr\u003e \u003cbr\u003e ESD Protection Design Methods\u003cbr\u003e \u003cbr\u003e Selecting an ESD Strategy\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 6 Design and Layout Requirements\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Thick Field Device\u003cbr\u003e \u003cbr\u003e NMOS Transistors (FPDs)\u003cbr\u003e \u003cbr\u003e Gate-Coupled NMOS (GCNMOS)\u003cbr\u003e \u003cbr\u003e Gate Driven nMOS (GDNMOS)\u003cbr\u003e \u003cbr\u003e SCR Protection Device\u003cbr\u003e \u003cbr\u003e ESD Protection Design Synthesis\u003cbr\u003e \u003cbr\u003e Total Input Protection\u003cbr\u003e \u003cbr\u003e ESD Protection Using Diode-Based Devices\u003cbr\u003e \u003cbr\u003e Power Supply Clamps\u003cbr\u003e \u003cbr\u003e BiPolar and BiCMOS Protection Circuits\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 7 Advanced Protection Design\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e PNP Driven NMOS (PDNMOS)\u003cbr\u003e \u003cbr\u003e Substrate Triggered NMOS (STNMOS)\u003cbr\u003e \u003cbr\u003e NMOS Triggered NMOS (NTNMOS)\u003cbr\u003e \u003cbr\u003e ESD for Mixed Voltage I\/O\u003cbr\u003e \u003cbr\u003e CDM Protection\u003cbr\u003e \u003cbr\u003e SOI Technology\u003cbr\u003e \u003cbr\u003e High Voltage Transistors\u003cbr\u003e \u003cbr\u003e BiCMOS Protection\u003cbr\u003e \u003cbr\u003e RF Designs\u003cbr\u003e \u003cbr\u003e General I\/O Protection Schemes\u003cbr\u003e \u003cbr\u003e Design\/layout Errors\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 8 Failure Modes, Reliability Issues, and Case Studies\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Failure Mode Analysis\u003cbr\u003e \u003cbr\u003e Reliability and Performance Considerations\u003cbr\u003e \u003cbr\u003e Advanced CMOS Input Protection\u003cbr\u003e \u003cbr\u003e Optimizing the Input Protection Scheme\u003cbr\u003e \u003cbr\u003e Designs for Special Applications\u003cbr\u003e \u003cbr\u003e Process Effects on Input Protection Design\u003cbr\u003e \u003cbr\u003e Total IC Chip Protection\u003cbr\u003e \u003cbr\u003e Power Bus Protection\u003cbr\u003e \u003cbr\u003e Internal Chip ESD Damage\u003cbr\u003e \u003cbr\u003e Stress Dependent ESD Behavior\u003cbr\u003e \u003cbr\u003e Failure Mode Case Studies\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 9 Influence of Processing on ESD\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e High Current Behavior\u003cbr\u003e \u003cbr\u003e Cross-section of a MOS Transistor\u003cbr\u003e \u003cbr\u003e Drain-Source Implant Effects\u003cbr\u003e \u003cbr\u003e P-Well Effects\u003cbr\u003e \u003cbr\u003e N-Well Effects\u003cbr\u003e \u003cbr\u003e Epitaxial Layers and Substrates\u003cbr\u003e \u003cbr\u003e Gate Oxides\u003cbr\u003e \u003cbr\u003e Silicides\u003cbr\u003e \u003cbr\u003e Contacts\u003cbr\u003e \u003cbr\u003e Interconnect and Metallization\u003cbr\u003e \u003cbr\u003e Gate Length Dependencies\u003cbr\u003e \u003cbr\u003e Silicon-On-Insulator (SOI)\u003cbr\u003e \u003cbr\u003e Bipolar Transistors\u003cbr\u003e \u003cbr\u003e Diodes\u003cbr\u003e \u003cbr\u003e Resistors\u003cbr\u003e \u003cbr\u003e Reliability Trade-Offs\u003cbr\u003e \u003cbr\u003e Summary\u003cbr\u003e \u003cbr\u003e 10 Device Modeling of High Current Effects\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e The Physics of ESD Damage\u003cbr\u003e \u003cbr\u003e Thermal (\"Second\") Breakdown\u003cbr\u003e \u003cbr\u003e Analytical Models Using the Heat Equation\u003cbr\u003e \u003cbr\u003e Electrothermal Device Simulations\u003cbr\u003e \u003cbr\u003e Conclusions\u003cbr\u003e \u003cbr\u003e Circuit Simulation Basics, Approaches, and Simulations\u003cbr\u003e \u003cbr\u003e Introduction\u003cbr\u003e \u003cbr\u003e Modeling the MOSFET\u003cbr\u003e \u003cbr\u003e Modeling Bipolar Junction Transistors\u003cbr\u003e \u003cbr\u003e Modeling Diffusion Resistors\u003cbr\u003e \u003cbr\u003e Modeling Protection Diodes\u003cbr\u003e \u003cbr\u003e Simulation of Protection Circuits\u003cbr\u003e \u003cbr\u003e Electrothermal Circuit Simulations\u003cbr\u003e \u003cbr\u003e Conclusion\u003cbr\u003e \u003cbr\u003e 12 Conclusions\u003cbr\u003e \u003cbr\u003e Long-term Relevance of ESD in ICs\u003cbr\u003e \u003cbr\u003e State-of-the-art for ESD Protection\u003cbr\u003e \u003cbr\u003e Current Limitations\u003cbr\u003e \u003cbr\u003e Future Issues  \u003cp\u003eE. Ajith Amerasekera is the author of ESD in Silicon Integrated Circuits, 2nd Edition, published by Wiley. Charvaka Duvvury is the author of ESD in Silicon Integrated Circuits, 2nd Edition, published by Wiley.  As high density circuits move deeper into submicron dimensions Electrostatic Discharge (ESD) effects become an increasing concern. This new edition of a classic reference presents a practical and systematic approach to ESD device physics, modelling and design techniques. The authors draw upon their wealth of industrial experience to provide a complete overview of ESD and its implications in the development of advanced integrated circuits.\u003cbr\u003e \u003cbr\u003e Fully revised to incorporate the latest industry achievements and featuring:\u003cbr\u003e * Design methods for a variety of technologies from 1 micron to the current sub-micron regimes, along with complete design approaches for MOS, BiCMOS and Power MOSFETs.\u003cbr\u003e \u003cbr\u003e * New sections on ESD design rules, process technology effects, layout approaches, package effects and circuit simulations.\u003cbr\u003e \u003cbr\u003e * Guidance on the implementation of circuit protection measures for a range of I\/O configurations.\u003cbr\u003e \u003cbr\u003e * Detailed coverage of ESD simulation stress models.\u003cbr\u003e This unique reference provides the means to design protection circuits for a variety of applications and to diagnose and solve ESD problems in IC products. The coverage of state-of-the-art circuit design for ESD prevention will appeal to engineers and scientists working in the fields of IC and transistor design. Graduate students and researchers in device\/circuit modeling and semiconductor reliability will appreciate this comprehensive coverage of ESD fundamentals.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47989153890533,"sku":"NP9780471498711","price":204.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780471498711.jpg?v=1761783014","url":"https:\/\/k12savings.com\/products\/esd-in-silicon-integrated-circuits-isbn-9780471498711","provider":"K12savings","version":"1.0","type":"link"}