{"product_id":"digital-system-clocking-isbn-9780471274476","title":"Digital System Clocking","description":"Provides the only up-to-date source on the most recent advances in this often complex and fascinating topic.  \u003cul\u003e \u003cli\u003eThe only book to be entirely devoted to clocking\u003c\/li\u003e \u003cli\u003eClocking has become one of the most important topics in the field of digital system design\u003c\/li\u003e \u003cli\u003eA \"must have\" book for advanced circuit engineers\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003ePreface xiii\u003c\/p\u003e \u003cp\u003eChapter 1 Introduction 1\u003c\/p\u003e \u003cp\u003eChapter 2 Theory of Clocked Storage Elements 27\u003c\/p\u003e \u003cp\u003eChapter 3 Timing and Energy Parameters 47\u003c\/p\u003e \u003cp\u003eChapter 4 Pipelining and Timing Analysis 63\u003c\/p\u003e \u003cp\u003eChapter 5 High-Performance System Issues 83\u003c\/p\u003e \u003cp\u003eChapter 6 Low-Energy System Issues 105\u003c\/p\u003e \u003cp\u003eChapter 7 Simulation Techniques 125\u003c\/p\u003e \u003cp\u003eChapter 8 State-of-the-Art Clocked Storage Elements in CMOS Technology 155\u003c\/p\u003e \u003cp\u003eChapter 9 Microprocesor Examples 189\u003c\/p\u003e \u003cp\u003eReferences 233\u003c\/p\u003e \u003cp\u003eIndex 241\u003c\/p\u003e  VOJIN G. OKLOBDZIJA received his PhD from the University of California, Los Angeles. He has been a consultant for major computer and electronics companies in the fields of high-performance systems, low-power design, and fast data-path implementations with the emphasis on multi-media applications and has published extensively on the subjects of system design and computer engineering. Dr. Oklobdzija has worked at the IBM T.J. Watson Research Center where he did pioneering work on RISC architecture and machine development starting with the IBM 801. Currently, he is a professor in the Department of Electrical and Computer Engineering at the University of California, Davis, where he directs the Advanced Computer Systems Engineering Laboratory (ACSEL).  \u003cp\u003eVLADIMIR M. STOJANOVIC is currently pursuing his PhD degree as a member of the VLSI research group, Electrical Engineering Department, Stanford University. He obtained MSEE degree from Stanford University and Dipl Ing diploma from Faculty of Electrical Engineering, University of Belgrade, Serbia. He was a research scholar at ACSEL.\u003c\/p\u003e \u003cp\u003eDEJAN M. MARKOVIC received an Dipl Ing degree in Electrical Engineering from the University of Belgrade, Yugoslavia, in 1998 and an MS in Electrical Engineering from the University of California at Berkeley in 2000, where he is currently working toward a PhD. Mr. Markovic received the 2000-2001 CalVIEW Fellow Award for excellence in teaching and mentoring of industry engineers through the UC Berkeley distant learning program. He is a current member of the UC Berkeley Hitachi Fellow Team, conducting market research on Hitachi?s Mu-Chip RFID technology.\u003c\/p\u003e \u003cp\u003eNIKOLA NEDOVIC is currently pursuing his PhD in the Department of Electrical and Computer Engineering at the University of California, Davis. He was a research scholar at ACSEL, and has been published in seven papers.\u003c\/p\u003e  Digital System Clocking is assuming ever greater importance as clock speeds increase, doubling every three years. This—the first book to focus entirely on clocked storage elements, \"Flip-Flops\" or \"Latches\"—provides an in-depth introduction to the subject for both professional computer design engineers and graduate-level computer engineering students. In Digital System Clocking: High-Performance and Low-Power Aspects, you will find information on: \u003cbr\u003e \u003cbr\u003e   \u003cul\u003e \u003cli\u003eClocking in synchronous systems including on-chip clock generation, timing parameters, and clock signal distribution\u003c\/li\u003e \u003cli\u003eLatch-based and Flip-Flop derivation\u003c\/li\u003e \u003cli\u003eClock-to-output delay tcq\u003c\/li\u003e \u003cli\u003ePipelining and timing analysis\u003c\/li\u003e \u003cli\u003eAbsorbing clock uncertaintites and dynamic time borrowing\u003c\/li\u003e \u003cli\u003eLow-swing circuit techniques, clock gating, and dual-edge triggering\u003c\/li\u003e \u003cli\u003eSimulation techniques including HLFF and M-SAFF sizing and CSE simulation bench in SPICE\u003c\/li\u003e \u003cli\u003eClocked storage elements in CMOS technology\u003c\/li\u003e \u003cli\u003eThe associated website provides materials for Instructors\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eWith numerous microprocessor examples including clocking for Intel®, Sun Microsystems’s UltraSPARC®-III, and IBM processors, Digital System Clocking: High-Performance and Low-Power Aspects provides much-needed answers about a technology that stands as a centerpiece of digital system design.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989068988645,"sku":"NP9780471274476","price":174.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780471274476.jpg?v=1761782666","url":"https:\/\/k12savings.com\/products\/digital-system-clocking-isbn-9780471274476","provider":"K12savings","version":"1.0","type":"link"}