{"product_id":"computer-architecture-and-security-isbn-9781118168813","title":"Computer Architecture and Security","description":"\u003cb\u003eThe first book to introduce computer architecture for security and provide the tools to implement secure computer systems\u003c\/b\u003e  \u003cp\u003eThis book provides the fundamentals of computer architecture for security. It covers a wide range of computer hardware, system software and data concepts from a security perspective. It is essential for computer science and security professionals to understand both hardware and software security solutions to survive in the workplace.\u003c\/p\u003e \u003cul\u003e \u003cli\u003eExamination of memory, CPU architecture and system implementation\u003c\/li\u003e \u003cli\u003eDiscussion of computer buses and a dual-port bus interface\u003c\/li\u003e \u003cli\u003eExamples cover a board spectrum of hardware and software systems\u003c\/li\u003e \u003cli\u003eDesign and implementation of a patent-pending secure computer system\u003c\/li\u003e \u003cli\u003eIncludes the latest patent-pending technologies in architecture security\u003c\/li\u003e \u003cli\u003ePlacement of computers in a security fulfilled network environment\u003c\/li\u003e \u003cli\u003eCo-authored by the inventor of the modern Computed Tomography (CT) scanner\u003c\/li\u003e \u003cli\u003eProvides website for lecture notes, security tools and latest updates\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eAbout the Authors xv\u003c\/p\u003e \u003cp\u003ePreface xvii\u003c\/p\u003e \u003cp\u003eAcknowledgements xix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction to Computer Architecture and Security 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 History of Computer Systems 3\u003c\/p\u003e \u003cp\u003e1.1.1 Timeline of Computer History 5\u003c\/p\u003e \u003cp\u003e1.1.2 Timeline of Internet History 15\u003c\/p\u003e \u003cp\u003e1.1.3 Timeline of Computer Security History 28\u003c\/p\u003e \u003cp\u003e1.2 John von Neumann Computer Architecture 34\u003c\/p\u003e \u003cp\u003e1.3 Memory and Storage 36\u003c\/p\u003e \u003cp\u003e1.4 Input\/Output and Network Interface 37\u003c\/p\u003e \u003cp\u003e1.5 Single CPU and Multiple CPU Systems 38\u003c\/p\u003e \u003cp\u003e1.6 Overview of Computer Security 41\u003c\/p\u003e \u003cp\u003e1.6.1 Confidentiality 41\u003c\/p\u003e \u003cp\u003e1.6.2 Integrity 42\u003c\/p\u003e \u003cp\u003e1.6.3 Availability 42\u003c\/p\u003e \u003cp\u003e1.6.4 Threats 43\u003c\/p\u003e \u003cp\u003e1.6.5 Firewalls 43\u003c\/p\u003e \u003cp\u003e1.6.6 Hacking and Attacks 44\u003c\/p\u003e \u003cp\u003e1.7 Security Problems in Neumann Architecture 46\u003c\/p\u003e \u003cp\u003e1.8 Summary 48\u003c\/p\u003e \u003cp\u003eExercises 48\u003c\/p\u003e \u003cp\u003eReferences 50\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Digital Logic Design 51\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Concept of Logic Unit 51\u003c\/p\u003e \u003cp\u003e2.2 Logic Functions and Truth Tables 52\u003c\/p\u003e \u003cp\u003e2.3 Boolean Algebra 54\u003c\/p\u003e \u003cp\u003e2.4 Logic Circuit Design Process 55\u003c\/p\u003e \u003cp\u003e2.5 Gates and Flip-Flops 56\u003c\/p\u003e \u003cp\u003e2.6 Hardware Security 58\u003c\/p\u003e \u003cp\u003e2.7 FPGA and VLSI 58\u003c\/p\u003e \u003cp\u003e2.7.1 Design of an FPGA Biometric Security System 59\u003c\/p\u003e \u003cp\u003e2.7.2 A RIFD Student Attendance System 59\u003c\/p\u003e \u003cp\u003e2.8 Summary 65\u003c\/p\u003e \u003cp\u003eExercises 67\u003c\/p\u003e \u003cp\u003eReferences 67\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Computer Memory and Storage 68\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 A One Bit Memory Circuit 68\u003c\/p\u003e \u003cp\u003e3.2 Register, MAR, MDR and Main Memory 70\u003c\/p\u003e \u003cp\u003e3.3 Cache Memory 72\u003c\/p\u003e \u003cp\u003e3.4 Virtual Memory 74\u003c\/p\u003e \u003cp\u003e3.4.1 Paged Virtual Memory\u003csup\u003e* \u003c\/sup\u003e75\u003c\/p\u003e \u003cp\u003e3.4.2 Segmented Virtual Memory\u003csup\u003e*\u003c\/sup\u003e 75\u003c\/p\u003e \u003cp\u003e3.5 Non-Volatile Memory 76\u003c\/p\u003e \u003cp\u003e3.6 External Memory 77\u003c\/p\u003e \u003cp\u003e3.6.1 Hard Disk Drives 78\u003c\/p\u003e \u003cp\u003e3.6.2 Tertiary Storage and Off-Line Storage\u003csup\u003e* \u003c\/sup\u003e78\u003c\/p\u003e \u003cp\u003e3.6.3 Serial Advanced Technology Attachment (SATA) 79\u003c\/p\u003e \u003cp\u003e3.6.4 Small Computer System Interface (SCSI) 80\u003c\/p\u003e \u003cp\u003e3.6.5 Serial Attached SCSI (SAS) 81\u003c\/p\u003e \u003cp\u003e3.6.6 Network-Attached Storage (NAS)\u003csup\u003e*\u003c\/sup\u003e 82\u003c\/p\u003e \u003cp\u003e3.6.7 Storage Area Network (SAN)\u003csup\u003e*\u003c\/sup\u003e 83\u003c\/p\u003e \u003cp\u003e3.6.8 Cloud Storage 85\u003c\/p\u003e \u003cp\u003e3.7 Memory Access Security 86\u003c\/p\u003e \u003cp\u003e3.8 Summary 88\u003c\/p\u003e \u003cp\u003eExercises 89\u003c\/p\u003e \u003cp\u003eReferences 89\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Bus and Interconnection 90\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 System Bus 90\u003c\/p\u003e \u003cp\u003e4.1.1 Address Bus 91\u003c\/p\u003e \u003cp\u003e4.1.2 Data Bus 93\u003c\/p\u003e \u003cp\u003e4.1.3 Control Bus 93\u003c\/p\u003e \u003cp\u003e4.2 Parallel Bus and Serial Bus 95\u003c\/p\u003e \u003cp\u003e4.2.1 Parallel Buses and Parallel Communication 95\u003c\/p\u003e \u003cp\u003e4.2.2 Serial Bus and Serial Communication 96\u003c\/p\u003e \u003cp\u003e4.3 Synchronous Bus and Asynchronous Bus 107\u003c\/p\u003e \u003cp\u003e4.4 Single Bus and Multiple Buses 109\u003c\/p\u003e \u003cp\u003e4.5 Interconnection Buses 110\u003c\/p\u003e \u003cp\u003e4.6 Security Considerations for Computer Buses 111\u003c\/p\u003e \u003cp\u003e4.7 A Dual-Bus Interface Design 112\u003c\/p\u003e \u003cp\u003e4.7.1 Dual-Channel Architecture\u003csup\u003e*\u003c\/sup\u003e 113\u003c\/p\u003e \u003cp\u003e4.7.2 Triple-Channel Architecture\u003csup\u003e*\u003c\/sup\u003e 114\u003c\/p\u003e \u003cp\u003e4.7.3 A Dual-Bus Memory Interface 115\u003c\/p\u003e \u003cp\u003e4.8 Summary 115\u003c\/p\u003e \u003cp\u003eExercises 117\u003c\/p\u003e \u003cp\u003eReferences 117\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 I\/O and Network Interface 118\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Direct Memory Access 118\u003c\/p\u003e \u003cp\u003e5.2 Interrupts 120\u003c\/p\u003e \u003cp\u003e5.3 Programmed I\/O 121\u003c\/p\u003e \u003cp\u003e5.4 USB and IEEE 1394 122\u003c\/p\u003e \u003cp\u003e5.4.1 USB Advantages 123\u003c\/p\u003e \u003cp\u003e5.4.2 USB Architecture 123\u003c\/p\u003e \u003cp\u003e5.4.3 USB Version History 124\u003c\/p\u003e \u003cp\u003e5.4.4 USB Design and Architecture\u003csup\u003e* \u003c\/sup\u003e125\u003c\/p\u003e \u003cp\u003e5.4.5 USB Mass Storage 127\u003c\/p\u003e \u003cp\u003e5.4.6 USB Interface Connectors 128\u003c\/p\u003e \u003cp\u003e5.4.7 USB Connector Types 130\u003c\/p\u003e \u003cp\u003e5.4.8 USB Power and Charging 133\u003c\/p\u003e \u003cp\u003e5.4.9 IEEE 1394 136\u003c\/p\u003e \u003cp\u003e5.5 Network Interface Card 136\u003c\/p\u003e \u003cp\u003e5.5.1 Basic NIC Architecture 137\u003c\/p\u003e \u003cp\u003e5.5.2 Data Transmission 138\u003c\/p\u003e \u003cp\u003e5.6 Keyboard, Video and Mouse (KVM) Interfaces 139\u003c\/p\u003e \u003cp\u003e5.6.1 Keyboards 140\u003c\/p\u003e \u003cp\u003e5.6.2 Video Graphic Card 140\u003c\/p\u003e \u003cp\u003e5.6.3 Mouses 140\u003c\/p\u003e \u003cp\u003e5.7 Input\/Output Security 140\u003c\/p\u003e \u003cp\u003e5.7.1 Disable Certain Key Combinations 141\u003c\/p\u003e \u003cp\u003e5.7.2 Anti-Glare Displays 141\u003c\/p\u003e \u003cp\u003e5.7.3 Adding Password to Printer 141\u003c\/p\u003e \u003cp\u003e5.7.4 Bootable USB Ports 141\u003c\/p\u003e \u003cp\u003e5.7.5 Encrypting Hard Drives 141\u003c\/p\u003e \u003cp\u003e5.8 Summary 141\u003c\/p\u003e \u003cp\u003eExercises 142\u003c\/p\u003e \u003cp\u003eReferences 143\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Central Processing Unit 144\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 The Instruction Set 144\u003c\/p\u003e \u003cp\u003e6.1.1 Instruction Classifications 144\u003c\/p\u003e \u003cp\u003e6.1.2 Logic Instructions 145\u003c\/p\u003e \u003cp\u003e6.1.3 Arithmetic Instructions 145\u003c\/p\u003e \u003cp\u003e6.1.4 Intel 64\/32 Instructions\u003csup\u003e* \u003c\/sup\u003e147\u003c\/p\u003e \u003cp\u003e6.2 Registers 153\u003c\/p\u003e \u003cp\u003e6.2.1 General-Purpose Registers 153\u003c\/p\u003e \u003cp\u003e6.2.2 Segment Registers 155\u003c\/p\u003e \u003cp\u003e6.2.3 EFLAGS Register 156\u003c\/p\u003e \u003cp\u003e6.3 The Program Counter and Flow Control 158\u003c\/p\u003e \u003cp\u003e6.3.1 Intel Instruction Pointer\u003csup\u003e* \u003c\/sup\u003e158\u003c\/p\u003e \u003cp\u003e6.3.2 Interrupt and Exception\u003csup\u003e*\u003c\/sup\u003e 159\u003c\/p\u003e \u003cp\u003e6.4 RISC Processors 161\u003c\/p\u003e \u003cp\u003e6.4.1 History 162\u003c\/p\u003e \u003cp\u003e6.4.2 Architecture and Programming 162\u003c\/p\u003e \u003cp\u003e6.4.3 Performance 163\u003c\/p\u003e \u003cp\u003e6.4.4 Advantages and Disadvantages 163\u003c\/p\u003e \u003cp\u003e6.4.5 Applications 164\u003c\/p\u003e \u003cp\u003e6.5 Pipelining 164\u003c\/p\u003e \u003cp\u003e6.5.1 Different Types of Pipelines 164\u003c\/p\u003e \u003cp\u003e6.5.2 Pipeline Performance Analysis 165\u003c\/p\u003e \u003cp\u003e6.5.3 Data Hazard 166\u003c\/p\u003e \u003cp\u003e6.6 CPU Security 166\u003c\/p\u003e \u003cp\u003e6.7 Virtual CPU 168\u003c\/p\u003e \u003cp\u003e6.8 Summary 169\u003c\/p\u003e \u003cp\u003eExercises 170\u003c\/p\u003e \u003cp\u003eReferences 170\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Advanced Computer Architecture 172\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Multiprocessors 172\u003c\/p\u003e \u003cp\u003e7.1.1 Multiprocessing 172\u003c\/p\u003e \u003cp\u003e7.1.2 Cache 173\u003c\/p\u003e \u003cp\u003e7.1.3 Hyper-Threading 174\u003c\/p\u003e \u003cp\u003e7.1.4 Symmetric Multiprocessing 175\u003c\/p\u003e \u003cp\u003e7.1.5 Multiprocessing Operating Systems 175\u003c\/p\u003e \u003cp\u003e7.1.6 The Future of Multiprocessing 176\u003c\/p\u003e \u003cp\u003e7.2 Parallel Processing 177\u003c\/p\u003e \u003cp\u003e7.2.1 History of Parallel Processing 177\u003c\/p\u003e \u003cp\u003e7.2.2 Flynn’s Taxonomy 178\u003c\/p\u003e \u003cp\u003e7.2.3 Bit-Level Parallelism 178\u003c\/p\u003e \u003cp\u003e7.2.4 Instruction-Level Parallelism 179\u003c\/p\u003e \u003cp\u003e7.2.5 Data-Level Parallelism 179\u003c\/p\u003e \u003cp\u003e7.2.6 Task-Level Parallelism 179\u003c\/p\u003e \u003cp\u003e7.2.7 Memory in Parallel Processing 180\u003c\/p\u003e \u003cp\u003e7.2.8 Specialized Parallel Computers 181\u003c\/p\u003e \u003cp\u003e7.2.9 The Future of Parallel Processing 182\u003c\/p\u003e \u003cp\u003e7.3 Ubiquitous Computing 182\u003c\/p\u003e \u003cp\u003e7.3.1 Ubiquitous Computing Development 183\u003c\/p\u003e \u003cp\u003e7.3.2 Basic forms of Ubiquitous Computing 184\u003c\/p\u003e \u003cp\u003e7.3.3 Augmented Reality 185\u003c\/p\u003e \u003cp\u003e7.3.4 Mobile Computing 186\u003c\/p\u003e \u003cp\u003e7.4 Grid, Distributed and Cloud Computing 187\u003c\/p\u003e \u003cp\u003e7.4.1 Characteristics of Grid Computing 187\u003c\/p\u003e \u003cp\u003e7.4.2 The Advantages and Disadvantages of Grid Computing 188\u003c\/p\u003e \u003cp\u003e7.4.3 Distributed Computing 189\u003c\/p\u003e \u003cp\u003e7.4.4 Distributed Systems 189\u003c\/p\u003e \u003cp\u003e7.4.5 Parallel and Distributed Computing 190\u003c\/p\u003e \u003cp\u003e7.4.6 Distributed Computing Architectures 190\u003c\/p\u003e \u003cp\u003e7.4.7 Cloud Computing 192\u003c\/p\u003e \u003cp\u003e7.4.8 Technical Aspects of Cloud Computing 193\u003c\/p\u003e \u003cp\u003e7.4.9 Security Aspects of Cloud Computing 194\u003c\/p\u003e \u003cp\u003e7.4.10 Ongoing and Future Elements in Cloud Computing 195\u003c\/p\u003e \u003cp\u003e7.4.11 Adoption of Cloud Computing Industry Drivers 196\u003c\/p\u003e \u003cp\u003e7.5 Internet Computing 197\u003c\/p\u003e \u003cp\u003e7.5.1 Internet Computing Concept and Model 198\u003c\/p\u003e \u003cp\u003e7.5.2 Benefit of Internet Computing for Businesses 199\u003c\/p\u003e \u003cp\u003e7.5.3 Examples of Internet Computing 201\u003c\/p\u003e \u003cp\u003e7.5.4 Migrating Internet Computing 202\u003c\/p\u003e \u003cp\u003e7.6 Virtualization 203\u003c\/p\u003e \u003cp\u003e7.6.1 Types of Virtualization 203\u003c\/p\u003e \u003cp\u003e7.6.2 History of Virtualization 205\u003c\/p\u003e \u003cp\u003e7.6.3 Virtualization Architecture 205\u003c\/p\u003e \u003cp\u003e7.6.4 Virtual Machine Monitor 207\u003c\/p\u003e \u003cp\u003e7.6.5 Examples of Virtual Machines 207\u003c\/p\u003e \u003cp\u003e7.7 Biocomputers 209\u003c\/p\u003e \u003cp\u003e7.7.1 Biochemical Computers 209\u003c\/p\u003e \u003cp\u003e7.7.2 Biomechanical Computers 209\u003c\/p\u003e \u003cp\u003e7.7.3 Bioelectronic Computers 210\u003c\/p\u003e \u003cp\u003e7.8 Summary 211\u003c\/p\u003e \u003cp\u003eExercises 212\u003c\/p\u003e \u003cp\u003eReferences 214\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Assembly Language and Operating Systems 216\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Assembly Language Basics 217\u003c\/p\u003e \u003cp\u003e8.1.1 Numbering Systems 217\u003c\/p\u003e \u003cp\u003e8.1.2 The Binary Numbering System and Base Conversions 219\u003c\/p\u003e \u003cp\u003e8.1.3 The Hexadecimal Numbering System 220\u003c\/p\u003e \u003cp\u003e8.1.4 Signed and Unsigned Numbers 221\u003c\/p\u003e \u003cp\u003e8.2 Operation Code and Operands 223\u003c\/p\u003e \u003cp\u003e8.3 Direct Addressing 225\u003c\/p\u003e \u003cp\u003e8.4 Indirect Addressing 225\u003c\/p\u003e \u003cp\u003e8.5 Stack and Buffer Overflow 226\u003c\/p\u003e \u003cp\u003e8.5.1 Calling Procedures Using CALL and RET (Return) 228\u003c\/p\u003e \u003cp\u003e8.5.2 Exploiting Stack Buffer Overflows 229\u003c\/p\u003e \u003cp\u003e8.5.3 Stack Protection 231\u003c\/p\u003e \u003cp\u003e8.6 FIFO and M\/M\/1 Problem 232\u003c\/p\u003e \u003cp\u003e8.6.1 FIFO Data Structure 232\u003c\/p\u003e \u003cp\u003e8.6.2 M\/M\/1 Model 233\u003c\/p\u003e \u003cp\u003e8.7 Kernel, Drivers and OS Security 234\u003c\/p\u003e \u003cp\u003e8.7.1 Kernel 234\u003c\/p\u003e \u003cp\u003e8.7.2 BIOS 235\u003c\/p\u003e \u003cp\u003e8.7.3 Boot Loader 236\u003c\/p\u003e \u003cp\u003e8.7.4 Device Drivers 237\u003c\/p\u003e \u003cp\u003e8.8 Summary 238\u003c\/p\u003e \u003cp\u003eExercises 239\u003c\/p\u003e \u003cp\u003eReferences 240\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 TCP\/IP and Internet 241\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Data Communications 241\u003c\/p\u003e \u003cp\u003e9.1.1 Signal, Data, and Channels 242\u003c\/p\u003e \u003cp\u003e9.1.2 Signal Encoding and Modulation 243\u003c\/p\u003e \u003cp\u003e9.1.3 Shannon Theorem 244\u003c\/p\u003e \u003cp\u003e9.2 TCP\/IP Protocol 244\u003c\/p\u003e \u003cp\u003e9.2.1 Network Topology 245\u003c\/p\u003e \u003cp\u003e9.2.2 Transmission Control Protocol (TCP) 246\u003c\/p\u003e \u003cp\u003e9.2.3 The User Datagram Protocol (UDP) 247\u003c\/p\u003e \u003cp\u003e9.2.4 Internet Protocol (IP) 247\u003c\/p\u003e \u003cp\u003e9.3 Network Switches 248\u003c\/p\u003e \u003cp\u003e9.3.1 Layer 1 Hubs 248\u003c\/p\u003e \u003cp\u003e9.3.2 Ethernet Switch 249\u003c\/p\u003e \u003cp\u003e9.4 Routers 250\u003c\/p\u003e \u003cp\u003e9.4.1 History of Routers 251\u003c\/p\u003e \u003cp\u003e9.4.2 Architecture 251\u003c\/p\u003e \u003cp\u003e9.4.3 Internet Protocol Version 4 (IPv4) 253\u003c\/p\u003e \u003cp\u003e9.4.4 Internet Protocol Version 6 (IPv6) 254\u003c\/p\u003e \u003cp\u003e9.4.5 Open Shortest Path First 254\u003c\/p\u003e \u003cp\u003e9.4.6 Throughput and Delay 256\u003c\/p\u003e \u003cp\u003e9.5 Gateways 257\u003c\/p\u003e \u003cp\u003e9.6 Wireless Networks and Network Address Translation (NAT) 258\u003c\/p\u003e \u003cp\u003e9.6.1 Wireless Networks 258\u003c\/p\u003e \u003cp\u003e9.6.2 Wireless Protocols 260\u003c\/p\u003e \u003cp\u003e9.6.3 WLAN Handshaking, War Driving, and WLAN Security 261\u003c\/p\u003e \u003cp\u003e9.6.4 Security Measures to Reduce Wireless Attacks 263\u003c\/p\u003e \u003cp\u003e9.6.5 The Future of Wireless Network 263\u003c\/p\u003e \u003cp\u003e9.6.6 Network Address Translation 264\u003c\/p\u003e \u003cp\u003e9.6.7 Environmental and Health Concerns Using Cellular and Wireless Devices 265\u003c\/p\u003e \u003cp\u003e9.7 Network Security 267\u003c\/p\u003e \u003cp\u003e9.7.1 Introduction 268\u003c\/p\u003e \u003cp\u003e9.7.2 Firewall Architecture 271\u003c\/p\u003e \u003cp\u003e9.7.3 Constraint and Limitations of Firewall 273\u003c\/p\u003e \u003cp\u003e9.7.4 Enterprise Firewalls 274\u003c\/p\u003e \u003cp\u003e9.8 Summary 275\u003c\/p\u003e \u003cp\u003eExercises 276\u003c\/p\u003e \u003cp\u003e9.9 Virtual Cyber-Security Laboratory 277\u003c\/p\u003e \u003cp\u003eReferences 278\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Design and Implementation: Modifying Neumann Architecture 280\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Data Security in Computer Systems 280\u003c\/p\u003e \u003cp\u003e10.1.1 Computer Security 281\u003c\/p\u003e \u003cp\u003e10.1.2 Data Security and Data Bleaches 282\u003c\/p\u003e \u003cp\u003e10.1.3 Researches in Architecture Security 283\u003c\/p\u003e \u003cp\u003e10.2 Single-Bus View of Neumann Architecture 284\u003c\/p\u003e \u003cp\u003e10.2.1 John von Neumann Computer Architecture 284\u003c\/p\u003e \u003cp\u003e10.2.2 Modified Neumann Computer Architecture 285\u003c\/p\u003e \u003cp\u003e10.2.3 Problems Exist in John Neumann Model 286\u003c\/p\u003e \u003cp\u003e10.3 A Dual-Bus Solution 286\u003c\/p\u003e \u003cp\u003e10.4 Bus Controller 288\u003c\/p\u003e \u003cp\u003e10.4.1 Working Mechanism of the Bus Controller 288\u003c\/p\u003e \u003cp\u003e10.4.2 Co-processor Board 289\u003c\/p\u003e \u003cp\u003e10.5 Dual-Port Storage 292\u003c\/p\u003e \u003cp\u003e10.6 Micro-Operating System 292\u003c\/p\u003e \u003cp\u003e10.7 Summary 293\u003c\/p\u003e \u003cp\u003eExercises 294\u003c\/p\u003e \u003cp\u003e10.8 Projects 295\u003c\/p\u003e \u003cp\u003eReferences 295\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A Digital Logic Simulators 297\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA.1 CEDAR Logic Simulator 297\u003c\/p\u003e \u003cp\u003eA.2 Logisim 298\u003c\/p\u003e \u003cp\u003eA.3 Digital Logic Simulator v0.4 298\u003c\/p\u003e \u003cp\u003eA.4 Logicly 299\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix B Computer Security Tools 300\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eB.1 Wireshark (Ethereal) 300\u003c\/p\u003e \u003cp\u003eB.2 Metasploit 300\u003c\/p\u003e \u003cp\u003eB.3 Nessus 301\u003c\/p\u003e \u003cp\u003eB.4 Aircrack 301\u003c\/p\u003e \u003cp\u003eB.5 Snort 301\u003c\/p\u003e \u003cp\u003eB.6 Cain and Abel 302\u003c\/p\u003e \u003cp\u003eB.7 BackTrack 302\u003c\/p\u003e \u003cp\u003eB.8 Netcat 302\u003c\/p\u003e \u003cp\u003eB.9 Tcpdump 302\u003c\/p\u003e \u003cp\u003eB.10 John the Ripper 303\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix C Patent Application: Intrusion-Free Computer Architecture for Information and Data Security 304\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eC.1 Background of the Invention 304\u003c\/p\u003e \u003cp\u003eC.1.1 John von Neumann Computer Architecture Model 305\u003c\/p\u003e \u003cp\u003eC.1.2 Modified Neumann Computer Architecture 305\u003c\/p\u003e \u003cp\u003eC.1.3 Problems Existed in the John Neumann Model 307\u003c\/p\u003e \u003cp\u003eC.1.4 The Goal of the Invention 307\u003c\/p\u003e \u003cp\u003eC.2 Field of Invention 308\u003c\/p\u003e \u003cp\u003eC.3 Detailed Description of the Invention 308\u003c\/p\u003e \u003cp\u003eC.4 Claim 310\u003c\/p\u003e \u003cp\u003eIndex 313\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eShuangbao (Paul) Wang,\u003c\/b\u003e \u003ci\u003eGeorge Mason University, USA\u003c\/i\u003e \u003c\/p\u003e\u003cp\u003e\u003cb\u003eRobert S. Ledley,\u003c\/b\u003e \u003ci\u003eGeorgetown University, USA\u003c\/i\u003e   \u003c\/p\u003e\u003cp\u003e\u003cb\u003eComputer Architecture and Security\u003cbr\u003e Fundamentals of Designing Secure Computer Systems\u003c\/b\u003e \u003c\/p\u003e\u003cp\u003eIn today's workplace, computer and information security professionals must understand both hardware and software to deploy effective security solutions. \u003cb\u003e\u003ci\u003eComputer Architecture and Security\u003c\/i\u003e\u003c\/b\u003e covers a wide range of computer and network hardware, system software, information and data concepts from a security perspective, providing readers with solutions and tools to implement secure computer and information systems. Featuring a careful, in-depth, and innovative introduction to modern computer systems and patent-pending technologies in computer security, the text integrates design considerations with hands-on experiences to help practitioners to render systems immune from attacks. \u003c\/p\u003e\u003cul\u003e \u003cli\u003e\u003cb\u003eExamination of memory, CPU architecture and system implementation\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003eDiscussion of computer buses and a dual-port bus interface\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003eExamples cover a board spectrum of hardware and software systems\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003eIncludes the latest patent-pending technologies in architecture security\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003ePlacement of computers in a security fulfilled network environment\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003eCo-authored by the inventor of the modern Computed Tomography (CT) scanner\u003c\/b\u003e\u003c\/li\u003e \u003cli\u003e\u003cb\u003eProvides Companion Website with lecture notes, security tools and latest updates\u003c\/b\u003e\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eThis book is geared for graduate students in computer architecture, communications, and information security, as well as engineers, researchers, security professionals, and middleware designers.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47988968521957,"sku":"NP9781118168813","price":138.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781118168813.jpg?v=1761782249","url":"https:\/\/k12savings.com\/products\/computer-architecture-and-security-isbn-9781118168813","provider":"K12savings","version":"1.0","type":"link"}