{"product_id":"advances-in-embedded-and-fan-out-wafer-level-packaging-technologies-isbn-9781119314134","title":"Advances in Embedded and Fan-Out Wafer Level Packaging Technologies","description":"\u003cp\u003e\u003cb\u003eExamines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eEmbedded and fan-out wafer level packaging (FO-WLP) technologies have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons.\u003c\/p\u003e \u003cp\u003eFilled with contributions from some of the field's leading experts,\u003ci\u003eAdvances in Embedded and Fan-Out Wafer Level Packaging Technologies\u003c\/i\u003e begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions.\u003c\/p\u003e \u003cul\u003e \u003cli\u003eDiscusses specific company standards and their development results\u003c\/li\u003e \u003cli\u003eContent relates to practice as well as to contemporary and future challenges in electronics system integration and packaging\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eAdvances in Embedded and Fan-Out Wafer Level Packaging Technologies\u003c\/i\u003e will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.\u003c\/p\u003e \u003cp\u003ePreface xvii\u003c\/p\u003e \u003cp\u003eList of Contributors xxiii\u003c\/p\u003e \u003cp\u003eAcknowledgments xxvii\u003c\/p\u003e \u003cp\u003e1 History of Embedded and Fan-Out Packaging Technology 1\u003ci\u003e\u003cbr\u003e\u003c\/i\u003e\u003ci\u003eMichael Topper, Andreas Ostmann, Tanja Braun, and Klaus-Dieter Lang\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2 FO-WLP Market and Technology Trends 39\u003ci\u003e\u003cbr\u003e\u003c\/i\u003e\u003ci\u003eE. Jan Vardaman\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3 Embedded Wafer-Level Ball Grid Array (eWLB) Packaging Technology Platform 55\u003ci\u003e\u003cbr\u003e\u003c\/i\u003e\u003ci\u003eThorsten Meyer and Steffen Krohnert\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4 Ultrathin 3D FO-WLP eWLB-PoP (Embedded Wafer-Level Ball Grid Array-Package-on-Package) Technology 77\u003cbr\u003e\u003ci\u003eS.W. Yoon\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5 NEPES’ Fan-Out Packaging Technology from Single die, SiP to Panel-Level Packaging 97\u003cbr\u003e\u003ci\u003eJong Heon (Jay) Kim\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6 M-Series Fan-Out with Adaptive Patterning 117\u003cbr\u003e\u003ci\u003eTim Olson and Chris Scanlan\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7 SWIFTR Semiconductor Packaging Technology 141\u003cbr\u003e\u003ci\u003eRon Huemoeller and Curtis Zwenger\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8 Embedded Silicon Fan-Out (eSiFOR) Technology for Wafer-Level System Integration 169\u003cbr\u003e\u003ci\u003eDaquan Yu\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9 Embedding of Active and Passive Devices by Using an Embedded Interposer: The i2 Board Technology 185\u003cbr\u003e\u003ci\u003eThomas Gottwald, Christian Roessle, and Alexander Neumann\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10 Embedding of Power Electronic Components: The Smart p2 Pack Technology 201\u003cbr\u003e\u003ci\u003eThomas Gottwald and Christian Roessle\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e11 Embedded Die in Substrate (Panel-Level) Packaging Technology 217\u003cbr\u003e\u003ci\u003eTomoko Takahashi and Akio Katsumata\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12 Blade: A Chip-First Embedded Technology for Power Packaging 241\u003cbr\u003e\u003ci\u003eBoris Plikat and Thorsten Scharf\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e13 The Role of Liquid Molding Compounds in the Success of Fan-Out Wafer-Level Packaging Technology 261\u003cbr\u003e\u003ci\u003eKatsushi Kan, Michiyasu Sugahara, and Markus Cichon\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e14 Advanced Dielectric Materials (Polyimides and Polybenzoxazoles) for Fan-Out Wafer-Level Packaging (FO-WLP) 271\u003cbr\u003e\u003ci\u003eT. Enomoto, J.I. Matthews, and T. Motobe\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e15 Enabling Low Temperature Cure Dielectrics for Advanced Wafer-Level Packaging 317\u003cbr\u003e\u003ci\u003eStefan Vanclooster and Dimitri Janssen\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e16 The Role of Pick and Place in Fan-Out Wafer-Level Packaging 347\u003cbr\u003e\u003ci\u003eHugo Pristauz, Alastair Attard, and Harald Meixner\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e17 Process and Equipment for eWLB: Chip Embedding by Molding 371\u003cbr\u003e\u003ci\u003eEdward Furgut, Hirohito Oshimori, and Hiroaki Yamagishi\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e18 Tools for Fan-Out Wafer-Level Package Processing 403\u003cbr\u003e\u003ci\u003eNelson Fan, Eric Kuah, Eric Ng, and Otto Cheung\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e19 Equipment and Process for eWLB: Required PVD\/Sputter Solutions 419\u003cbr\u003e\u003ci\u003eChris Jones, Ricardo Gaio, and Jose Castro\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e20 Excimer Laser Ablation for the Patterning of Ultra-fine Routings 441\u003cbr\u003e\u003ci\u003eHabib Hichri, Markus Arendt, and Seongkuk Lee\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e21 Temporary Carrier Technologies for eWLB and RDL-First Fan-Out Wafer-Level Packages 457\u003cbr\u003e\u003ci\u003eThomas Uhrmann and Boris Považay\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e22 Encapsulated Wafer-Level Package Technology (eWLCSP): Robust WLCSP Reliability with Sidewall Protection 471\u003cbr\u003e\u003ci\u003eS.W. Yoon\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e23 Embedded Multi-die Interconnect Bridge (EMIB): A Localized, High Density, High Bandwidth Packaging Interconnect 487\u003cbr\u003e\u003ci\u003eRavi Mahajan, Robert Sankman, Kemal Aygun, Zhiguo Qian, Ashish Dhall, Jonathan Rosch, Debendra Mallik, and Islam Salama\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e24 Interconnection Technology Innovations in 2.5D Integrated Electronic Systems 501\u003cbr\u003e\u003ci\u003eParagkumar A. Thadesar, Paul K. Jo, and Muhannad S. Bakir\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eReferences \u003ci\u003e515\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eIndex \u003ci\u003e521\u003c\/i\u003e\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eBeth Keser, Ph.D.,\u003c\/b\u003e is a recognized global leader in the semiconductor industry with over 20 years' experience resulting in 28 patents and patents pending and over 40 publications. She is an IEEE Senior Member whose volunteer activities and professional society responsibilities include: IEEE EPS' VP of Education, 2015 ECTC General Chair, and more. \u003c\/p\u003e\u003cp\u003e\u003cb\u003eSteffen Kröhnert, M.S\u003csmall\u003eC\u003c\/small\u003e.,\u003c\/b\u003e is Senior Director of Technology Development at Amkor Technology Holding B.V., Germany. He has more than 20 years' experience in the semiconductor industry. Steffen is author and co-author of 23 patent filings in the area of Semiconductor Packaging Technology, and an active member of IEEE EPS, IMAPS, SMTA, VDI, VDE and GPM.\t   \u003c\/p\u003e\u003cp\u003e\u003cb\u003eExamines the advantages of Embedded and FO-WLP technologies, potential application spaces, package structures available in the industry, process flows, and material challenges\u003c\/b\u003e\t \u003c\/p\u003e\u003cp\u003e\u003ci\u003eEmbedded and fan-out wafer level packaging\u003c\/i\u003e (FO-WLP) \u003ci\u003etechnologies\u003c\/i\u003e have been developed across the industry over the past 15 years and have been in high volume manufacturing for nearly a decade. This book covers the advances that have been made in this new packaging technology and discusses the many benefits it provides to the electronic packaging industry and supply chain. It provides a compact overview of the major types of technologies offered in this field, on what is available, how it is processed, what is driving its development, and the pros and cons. \u003c\/p\u003e\u003cp\u003eFilled with contributions from some of the field's leading experts,\u003ci\u003e??Advances in Embedded and Fan-Out Wafer Level Packaging Technologies\u003c\/i\u003e??begins with a look at the history of the technology. It then goes on to examine the biggest technology and marketing trends. Other sections are dedicated to chip-first FO-WLP, chip-last FO-WLP, embedded die packaging, materials challenges, equipment challenges, and resulting technology fusions. This valuable text: \u003c\/p\u003e\u003cul\u003e \u003cli\u003eDiscusses specific company standards and their development results\u003c\/li\u003e \u003cli\u003eRelates its content to practice as well as to contemporary and future challenges in electronics system integration and packaging\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eAdvances in Embedded and Fan-Out Wafer Level Packaging Technologie\u003c\/i\u003es??will appeal to microelectronic packaging engineers, managers, and decision makers working in OEMs, IDMs, IFMs, OSATs, silicon foundries, materials suppliers, equipment suppliers, and CAD tool suppliers. It is also an excellent book for professors and graduate students working in microelectronic packaging research.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47988677771493,"sku":"NP9781119314134","price":150.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781119314134.jpg?v=1761781222","url":"https:\/\/k12savings.com\/products\/advances-in-embedded-and-fan-out-wafer-level-packaging-technologies-isbn-9781119314134","provider":"K12savings","version":"1.0","type":"link"}