{"product_id":"advanced-interconnects-for-ulsi-technology-isbn-9780470662540","title":"Advanced Interconnects for ULSI Technology","description":"Finding new materials for copper\/low-k interconnects is critical to the continuing development of computer chips. While copper\/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.  \u003cp\u003e\u003ci\u003eAdvanced Interconnects for ULSI Technology\u003c\/i\u003e is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eInterconnect functions, characterisations, electrical properties and wiring requirements\u003c\/li\u003e \u003cli\u003eLow-k materials: fundamentals, advances and mechanical  properties\u003c\/li\u003e \u003cli\u003eConductive layers and barriers\u003c\/li\u003e \u003cli\u003eIntegration and reliability including mechanical reliability, electromigration and electrical breakdown\u003c\/li\u003e \u003cli\u003eNew approaches including 3D, optical, wireless interchip, and carbon-based interconnects\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eIntended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.\u003c\/p\u003eFinding new materials for copper\/low-k interconnects is critical to the continuing development of computer chips. While copper\/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance. Advanced Interconnects for ULSI Technology is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses: *Interconnect functions, characterisations, electrical properties and wiring requirements *Low-k materials: fundamentals, advances and mechanical  properties *Conductive layers and barriers *Integration and reliability including mechanical reliability, electromigration and electrical breakdown *New approaches including 3D, optical, wireless interchip, and carbon-based interconnects Intended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.  \u003cb\u003e\u003ci\u003eAbout the Editors\u003c\/i\u003e xv\u003c\/b\u003e  \u003cp\u003e\u003cb\u003e\u003ci\u003eList of Contributors\u003c\/i\u003e xvii\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e\u003ci\u003ePreface\u003c\/i\u003e xxi\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e\u003ci\u003eList of Abbreviations\u003c\/i\u003e xxv\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSection I Low-\u003ci\u003ek\u003c\/i\u003e Materials 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Low-\u003ci\u003ek\u003c\/i\u003e Materials: Recent Advances 3\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eGeraud Dubois and Willi Volksen\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1 Introduction 3\u003c\/p\u003e \u003cp\u003e1.2 Integration Challenges 5\u003c\/p\u003e \u003cp\u003e1.2.1 Process-Induced Damage 6\u003c\/p\u003e \u003cp\u003e1.2.2 Mechanical Properties 9\u003c\/p\u003e \u003cp\u003e1.3 Processing Approaches to Existing Integration Issues 10\u003c\/p\u003e \u003cp\u003e1.3.1 Post-deposition Treatments 11\u003c\/p\u003e \u003cp\u003e1.3.2 Prevention or Repair of Plasma-Induced Processing Damage 14\u003c\/p\u003e \u003cp\u003e1.3.3 Multilayer Structures 15\u003c\/p\u003e \u003cp\u003e1.4 Material Advances to Overcome Current Limitations 16\u003c\/p\u003e \u003cp\u003e1.4.1 Silica Zeolites 16\u003c\/p\u003e \u003cp\u003e1.4.2 Hybrid Organic–Inorganic: Oxycarbosilanes 19\u003c\/p\u003e \u003cp\u003e1.5 Conclusion 22\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Ultra-Low-\u003ci\u003ek\u003c\/i\u003e by CVD: Deposition and Curing 35\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eVincent Jousseaume, Aziz Zenasni, Olivier Gourhant,\u003c\/i\u003e \u003ci\u003eLaurent Favennec and Mikhail R. Baklanov\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1 Introduction 35\u003c\/p\u003e \u003cp\u003e2.2 Porogen Approach by PECVD 37\u003c\/p\u003e \u003cp\u003e2.2.1 Precursors and Deposition Conditions 37\u003c\/p\u003e \u003cp\u003e2.2.2 Mystery Still Unsolved: From Porogens to Pores 41\u003c\/p\u003e \u003cp\u003e2.3 UV Curing 42\u003c\/p\u003e \u003cp\u003e2.3.1 General Overview of Curing 42\u003c\/p\u003e \u003cp\u003e2.3.2 UV Curing Mechanisms 43\u003c\/p\u003e \u003cp\u003e2.4 Impact of Curing on Structure and Physical Properties: Benefits of UV Curing 49\u003c\/p\u003e \u003cp\u003e2.4.1 Porosity 49\u003c\/p\u003e \u003cp\u003e2.4.2 Chemical Structure and Mechanical Properties 50\u003c\/p\u003e \u003cp\u003e2.4.3 Electrical Properties 56\u003c\/p\u003e \u003cp\u003e2.5 Limit\/Issues with the Porogen Approach 57\u003c\/p\u003e \u003cp\u003e2.5.1 Porosity Creation Limit 58\u003c\/p\u003e \u003cp\u003e2.5.2 Porogen Residues 59\u003c\/p\u003e \u003cp\u003e2.6 Future of CVD Low-\u003ci\u003ek\u003c\/i\u003e 62\u003c\/p\u003e \u003cp\u003e2.6.1 New Matrix Precursor 62\u003c\/p\u003e \u003cp\u003e2.6.2 Other Deposition Strategies 64\u003c\/p\u003e \u003cp\u003e2.6.3 New Deposition Techniques 66\u003c\/p\u003e \u003cp\u003e2.7 Material Engineering: Adaptation to Integration Schemes 68\u003c\/p\u003e \u003cp\u003e2.8 Conclusion 70\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Plasma Processing of Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 79\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eHualing Shi, Denis Shamiryan, Jean-Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction 79\u003c\/p\u003e \u003cp\u003e3.2 Materials and Equipment 80\u003c\/p\u003e \u003cp\u003e3.3 Process Results Characterization 82\u003c\/p\u003e \u003cp\u003e3.4 Interaction of Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics with Plasma 85\u003c\/p\u003e \u003cp\u003e3.4.1 Low-\u003ci\u003ek\u003c\/i\u003e Etch Chemistries 85\u003c\/p\u003e \u003cp\u003e3.4.2 Patterning Strategies and Masking Materials 87\u003c\/p\u003e \u003cp\u003e3.4.3 Etch Mechanisms 88\u003c\/p\u003e \u003cp\u003e3.5 Mechanisms of Plasma Damage 92\u003c\/p\u003e \u003cp\u003e3.5.1 Gap Structure Studies 93\u003c\/p\u003e \u003cp\u003e3.5.2 Effect of Radical Density 95\u003c\/p\u003e \u003cp\u003e3.5.3 Effect of Ion Energy 96\u003c\/p\u003e \u003cp\u003e3.5.4 Effect of Photon Energy and Intensity 99\u003c\/p\u003e \u003cp\u003e3.5.5 Plasma Damage by Oxidative Radicals 103\u003c\/p\u003e \u003cp\u003e3.5.6 Hydrogen-Based Plasma 105\u003c\/p\u003e \u003cp\u003e3.5.7 Minimization of Plasma Damage 108\u003c\/p\u003e \u003cp\u003e3.6 Dielectric Recovery 112\u003c\/p\u003e \u003cp\u003e3.6.1 CH4 Beam Treatment 112\u003c\/p\u003e \u003cp\u003e3.6.2 Dielectric Recovery by Silylation 113\u003c\/p\u003e \u003cp\u003e3.6.3 UV Radiation 119\u003c\/p\u003e \u003cp\u003e3.7 Conclusions 121\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Wet Clean Applications in Porous Low-\u003ci\u003ek\u003c\/i\u003e Patterning Processes 129\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eQuoc Toan Le, Guy Vereecke, Herbert Struyf, Els Kesters\u003c\/i\u003e \u003ci\u003eand Mikhail R. Baklanov\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1 Introduction 129\u003c\/p\u003e \u003cp\u003e4.2 Silica and Porous Hybrid Dielectric Materials 130\u003c\/p\u003e \u003cp\u003e4.3 Impact of Plasma and Subsequent Wet Clean Processes on the Stability of Porous Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 134\u003c\/p\u003e \u003cp\u003e4.3.1 Stability in Pure Chemical Solutions 134\u003c\/p\u003e \u003cp\u003e4.3.2 Stability in Commercial Chemistries 135\u003c\/p\u003e \u003cp\u003e4.3.3 Hydrophobicity of Hybrid Low-\u003ci\u003ek\u003c\/i\u003e Materials 138\u003c\/p\u003e \u003cp\u003e4.4 Removal of Post-Etch Residues and Copper Surface Cleaning 141\u003c\/p\u003e \u003cp\u003e4.5 Plasma Modification and Removal of Post-Etch 193 nm Photoresist 146\u003c\/p\u003e \u003cp\u003e4.5.1 Modification of 193 nm Photoresist by Plasma Etch 146\u003c\/p\u003e \u003cp\u003e4.5.2 Wet Removal of 193 nm Photoresist 153\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSection II Conductive Layers and Barriers 173\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Copper Electroplating for On-Chip Metallization 175\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eValery M. Dubin\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 175\u003c\/p\u003e \u003cp\u003e5.2 Copper Electroplating Techniques 176\u003c\/p\u003e \u003cp\u003e5.3 Copper Electroplating Superfill 177\u003c\/p\u003e \u003cp\u003e5.3.1 The Role of Accelerator 177\u003c\/p\u003e \u003cp\u003e5.3.2 The Role of Suppressor 178\u003c\/p\u003e \u003cp\u003e5.3.3 The Role of Leveler 180\u003c\/p\u003e \u003cp\u003e5.4 Alternative Cu Plating Methods 182\u003c\/p\u003e \u003cp\u003e5.4.1 Electroless Plating 182\u003c\/p\u003e \u003cp\u003e5.4.2 Direct Plating 182\u003c\/p\u003e \u003cp\u003e5.5 Electroplated Cu Properties 184\u003c\/p\u003e \u003cp\u003e5.5.1 Resistivity 184\u003c\/p\u003e \u003cp\u003e5.5.2 Impurities 184\u003c\/p\u003e \u003cp\u003e5.5.3 Electromigration 185\u003c\/p\u003e \u003cp\u003e5.6 Conclusions 186\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Diffusion Barriers 193\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eMichael Hecker and René Hübner\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 193\u003c\/p\u003e \u003cp\u003e6.1.1 Cu Metallization, Barrier Requirements and Materials 193\u003c\/p\u003e \u003cp\u003e6.1.2 Barrier Deposition Techniques 195\u003c\/p\u003e \u003cp\u003e6.1.3 Characterization of Barrier Performance 196\u003c\/p\u003e \u003cp\u003e6.2 Metal-Based Barriers as Liners for Cu Seed Deposition 198\u003c\/p\u003e \u003cp\u003e6.2.1 Ta-Based Barriers 198\u003c\/p\u003e \u003cp\u003e6.2.2 W-Based Barriers 209\u003c\/p\u003e \u003cp\u003e6.2.3 Ti-Based Barriers 210\u003c\/p\u003e \u003cp\u003e6.2.4 Further Systems 211\u003c\/p\u003e \u003cp\u003e6.3 Advanced Barrier Approaches 212\u003c\/p\u003e \u003cp\u003e6.3.1 Barriers for Direct Cu Plating 212\u003c\/p\u003e \u003cp\u003e6.3.2 Metal Capping Layers 214\u003c\/p\u003e \u003cp\u003e6.3.3 Self-Forming Diffusion Barriers 216\u003c\/p\u003e \u003cp\u003e6.3.4 Self-Assembled Molecular Nanolayers and Polymer-Based Barriers 218\u003c\/p\u003e \u003cp\u003e6.4 Conclusions 221\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSection III Integration and Reliability 235\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Integration and Electrical Properties 237\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eSridhar Balakrishnan, Ruth Brain and Larry Zhao\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction 237\u003c\/p\u003e \u003cp\u003e7.2 On-Die Interconnects in the Submicrometer Era 237\u003c\/p\u003e \u003cp\u003e7.3 On-Die Interconnects at Sub-100 nm Nodes 240\u003c\/p\u003e \u003cp\u003e7.4 Integration of Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics in Sub-65 nm Nodes 241\u003c\/p\u003e \u003cp\u003e7.4.1 Degradation of Dielectric Constant during Integration 243\u003c\/p\u003e \u003cp\u003e7.4.2 Integration Issues in ELK Dielectrics Due to Degraded Mechanical Properties 246\u003c\/p\u003e \u003cp\u003e7.5 Patterning Integration at Sub-65 nm Nodes 248\u003c\/p\u003e \u003cp\u003e7.5.1 Patterning Challenges 249\u003c\/p\u003e \u003cp\u003e7.6 Integration of Conductors in Sub-65 nm Nodes 252\u003c\/p\u003e \u003cp\u003e7.6.1 Narrow Line Copper Resistivity 253\u003c\/p\u003e \u003cp\u003e7.6.2 Integrating Novel Barrier\/Liner Materials and Deposition Techniques for Cu Interconnects 254\u003c\/p\u003e \u003cp\u003e7.6.3 Self-Forming Barriers and Their Integration 256\u003c\/p\u003e \u003cp\u003e7.6.4 Integration to Enable Reliable Copper Interconnects 257\u003c\/p\u003e \u003cp\u003e7.7 Novel Air-Gap Interconnects 258\u003c\/p\u003e \u003cp\u003e7.7.1 Unlanded Via Integration with Air-Gap Interconnects 258\u003c\/p\u003e \u003cp\u003e7.7.2 Air-Gap Formation Using Nonconformal Dielectric Deposition 259\u003c\/p\u003e \u003cp\u003e7.7.3 Air-Gap Formation Using a Sacrificial Material 260\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Chemical Mechanical Planarization for Cu–Low-\u003ci\u003ek\u003c\/i\u003e Integration 267\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eGautam Banerjee\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction 267\u003c\/p\u003e \u003cp\u003e8.2 Back to Basics 268\u003c\/p\u003e \u003cp\u003e8.3 Mechanism of the CMP Process 268\u003c\/p\u003e \u003cp\u003e8.4 CMP Consumables 271\u003c\/p\u003e \u003cp\u003e8.4.1 Slurry 271\u003c\/p\u003e \u003cp\u003e8.4.2 Pad 273\u003c\/p\u003e \u003cp\u003e8.4.3 Pad Conditioner 274\u003c\/p\u003e \u003cp\u003e8.5 CMP Interactions 276\u003c\/p\u003e \u003cp\u003e8.6 Post-CMP Cleaning 281\u003c\/p\u003e \u003cp\u003e8.6.1 Other Defects 286\u003c\/p\u003e \u003cp\u003e8.6.2 Surface Finish 286\u003c\/p\u003e \u003cp\u003e8.6.3 E-Test 287\u003c\/p\u003e \u003cp\u003e8.7 Future Direction 287\u003c\/p\u003e \u003cp\u003eReferences 288\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Scaling and Microstructure Effects on Electromigration Reliability\u003c\/b\u003e \u003cb\u003efor Cu Interconnects 291\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eChao-Kun Hu, René Hübner, Lijuan Zhang,\u003c\/i\u003e \u003ci\u003eMeike Hauschildt and Paul S. Ho\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction 291\u003c\/p\u003e \u003cp\u003e9.2 Electromigration Fundamentals 293\u003c\/p\u003e \u003cp\u003e9.2.1 EM Mass Flow 293\u003c\/p\u003e \u003cp\u003e9.2.2 EM Lifetime and Scaling Rule 294\u003c\/p\u003e \u003cp\u003e9.2.3 Statistical Test Method 296\u003c\/p\u003e \u003cp\u003e9.2.4 Effect of Current Density on EM Lifetime 298\u003c\/p\u003e \u003cp\u003e9.3 Cu Microstructure 300\u003c\/p\u003e \u003cp\u003e9.3.1 X-ray Diffraction (XRD) 300\u003c\/p\u003e \u003cp\u003e9.3.2 Electron Backscatter Diffraction in the Scanning Electron Microscope 302\u003c\/p\u003e \u003cp\u003e9.3.3 Orientation Imaging Microscopy in the Transmission Electron Microscope 304\u003c\/p\u003e \u003cp\u003e9.4 Lifetime Enhancement 306\u003c\/p\u003e \u003cp\u003e9.4.1 Effect of a Ta Liner 306\u003c\/p\u003e \u003cp\u003e9.4.2 Upper-Level Dummy Vias 308\u003c\/p\u003e \u003cp\u003e9.4.3 Plasma Pre-clean and SiH4 Soak 310\u003c\/p\u003e \u003cp\u003e9.4.4 CVD and ECD Cu and the Effect of Nonmetallic Impurities 311\u003c\/p\u003e \u003cp\u003e9.4.5 Cu Alloys 314\u003c\/p\u003e \u003cp\u003e9.4.6 CoWP Cap Near-Bamboo and Polycrystalline Cu Lines 319\u003c\/p\u003e \u003cp\u003e9.5 Effect of Grain Size on EM Lifetime and Statistics 321\u003c\/p\u003e \u003cp\u003e9.6 Massive-Scale Statistical Study of EM 326\u003c\/p\u003e \u003cp\u003e9.7 Summary 329\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Mechanical Reliability of Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 339\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eKris Vanstreels, Han Li and Joost J. Vlassak\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction 339\u003c\/p\u003e \u003cp\u003e10.2 Mechanical Properties of Porous Low-\u003ci\u003ek\u003c\/i\u003e Materials 340\u003c\/p\u003e \u003cp\u003e10.2.1 Techniques to Measure Mechanical Properties of Thin Films 340\u003c\/p\u003e \u003cp\u003e10.2.2 Effect of Porosity on the Stiffness of Organosilicate Glass Films 342\u003c\/p\u003e \u003cp\u003e10.2.3 Hybrid Dielectrics Containing Organic\/Inorganic Bridging Units 344\u003c\/p\u003e \u003cp\u003e10.2.4 Effect of UV Wavelength and Porogen Content on the Hardening Process of PECVD Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 349\u003c\/p\u003e \u003cp\u003e10.3 Fracture Properties of Porous Low-\u003ci\u003ek\u003c\/i\u003e Materials 352\u003c\/p\u003e \u003cp\u003e10.3.1 Adhesion Measurement Methods 352\u003c\/p\u003e \u003cp\u003e10.3.2 Fracture Toughness Measurement Techniques 354\u003c\/p\u003e \u003cp\u003e10.3.3 Effect of Porosity and Network Structure on the Fracture Toughness of Organosilicate Glass Films 355\u003c\/p\u003e \u003cp\u003e10.3.4 Effects of UV Cure on Fracture Properties of Carbon-Doped Oxides 357\u003c\/p\u003e \u003cp\u003e10.3.5 Water Diffusion and Fracture Properties of Organosilicate Glass Films 359\u003c\/p\u003e \u003cp\u003e10.4 Conclusion 361\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Electrical Breakdown in Advanced Interconnect Dielectrics 369\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eEnnis T. Ogawa and Oliver Aubel\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 369\u003c\/p\u003e \u003cp\u003e11.1.1 Dual-Damascene Integration of Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 370\u003c\/p\u003e \u003cp\u003e11.1.2 Low-\u003ci\u003ek\u003c\/i\u003e Types and Integrating Low-\u003ci\u003ek\u003c\/i\u003e Dielectrics 373\u003c\/p\u003e \u003cp\u003e11.2 Reliability Testing 378\u003c\/p\u003e \u003cp\u003e11.2.1 Measurement of Dielectric Degradation 378\u003c\/p\u003e \u003cp\u003e11.2.2 Reliability Analysis 390\u003c\/p\u003e \u003cp\u003e11.3 Lifetime Extrapolation and Models 397\u003c\/p\u003e \u003cp\u003e11.4 Future Trends and Concerns 403\u003c\/p\u003e \u003cp\u003e\u003cb\u003eSection IV New Approaches 435\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 3D Interconnect Technology 437\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eJohn U. Knickerbocker, Lay Wai Kong, Sven Niese,\u003c\/i\u003e \u003ci\u003eAlain Diebold and Ehrenfried Zschech\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction 437\u003c\/p\u003e \u003cp\u003e12.2 Dimensional Interconnected Circuits (3DICs) for System Applications 438\u003cbr\u003e \u003ci\u003eJohn U. Knickerbocker\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12.2.1 Introduction 438\u003c\/p\u003e \u003cp\u003e12.2.2 System Needs 441\u003c\/p\u003e \u003cp\u003e12.2.3 3D Interconnect Design and Architecture 444\u003c\/p\u003e \u003cp\u003e12.2.4 3D Fabrication and Interconnect Technology 446\u003c\/p\u003e \u003cp\u003e12.2.5 Trade-offs in Application Design and Product Applications 464\u003c\/p\u003e \u003cp\u003e12.2.6 Summary 466\u003c\/p\u003e \u003cp\u003e12.3 Advanced Microscopy Techniques for 3D Interconnect Characterization 467\u003cbr\u003e \u003ci\u003eLay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12.3.1 Scanning Acoustic Microscopy 467\u003c\/p\u003e \u003cp\u003e12.3.2 IR Microscopy 473\u003c\/p\u003e \u003cp\u003e12.3.3 Transmission X-ray Microscopy and Tomography 474\u003c\/p\u003e \u003cp\u003e12.3.4 Microstructure Analysis 480\u003c\/p\u003e \u003cp\u003e12.4 Summary 486\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Carbon Nanotubes for Interconnects 491\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eMizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato\u003c\/i\u003e \u003ci\u003eand Yuji Awano\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e13.1 Introduction 491\u003c\/p\u003e \u003cp\u003e13.2 Advantage of CNT Vias 492\u003c\/p\u003e \u003cp\u003e13.3 Fabrication Processes of CNT Vias 493\u003c\/p\u003e \u003cp\u003e13.4 Electrical Properties of CNT Vias 496\u003c\/p\u003e \u003cp\u003e13.5 Current Reliability of CNT Vias 498\u003c\/p\u003e \u003cp\u003e13.6 Conclusion 501\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Optical Interconnects 503\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eWim Bogaerts\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction 503\u003c\/p\u003e \u003cp\u003e14.2 Optical Links 505\u003c\/p\u003e \u003cp\u003e14.2.1 Waveguides 507\u003c\/p\u003e \u003cp\u003e14.2.2 Waveguide Filters and (De)multiplexers 510\u003c\/p\u003e \u003cp\u003e14.2.3 Transmitter: Light Source 513\u003c\/p\u003e \u003cp\u003e14.2.4 Transmitter: Modulators 514\u003c\/p\u003e \u003cp\u003e14.2.5 Receiver: Photodetector 517\u003c\/p\u003e \u003cp\u003e14.2.6 Power Consumption and Heat Dissipation 517\u003c\/p\u003e \u003cp\u003e14.2.7 Different Materials 518\u003c\/p\u003e \u003cp\u003e14.2.8 Conclusion 519\u003c\/p\u003e \u003cp\u003e14.3 The Case for Silicon Photonics 519\u003c\/p\u003e \u003cp\u003e14.3.1 Waveguides and WDM Components 519\u003c\/p\u003e \u003cp\u003e14.3.2 Modulators, Tuners and Switches 523\u003c\/p\u003e \u003cp\u003e14.3.3 Photodetectors 526\u003c\/p\u003e \u003cp\u003e14.3.4 Light Sources 526\u003c\/p\u003e \u003cp\u003e14.3.5 Conclusion 527\u003c\/p\u003e \u003cp\u003e14.4 Optical Networks on a Chip 528\u003c\/p\u003e \u003cp\u003e14.4.1 WDM Point-to-Point Links 529\u003c\/p\u003e \u003cp\u003e14.4.2 Bus Architecture 529\u003c\/p\u003e \u003cp\u003e14.4.3 (Reconfigurable) Networks 530\u003c\/p\u003e \u003cp\u003e14.5 Integration Strategies 532\u003c\/p\u003e \u003cp\u003e14.5.1 Front-End-of-Line Integration 533\u003c\/p\u003e \u003cp\u003e14.5.2 Backside Integration 535\u003c\/p\u003e \u003cp\u003e14.5.3 Back-End-of-Line Integration 535\u003c\/p\u003e \u003cp\u003e14.5.4 3D Integration 536\u003c\/p\u003e \u003cp\u003e14.5.5 Flip-Chip Integration 537\u003c\/p\u003e \u003cp\u003e14.5.6 Conclusion 537\u003c\/p\u003e \u003cp\u003e14.6 Conclusion 538\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Wireless Interchip Interconnects 543\u003cbr\u003e \u003c\/b\u003e\u003ci\u003eTakamaro Kikkawa\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e15.1 Introduction 543\u003c\/p\u003e \u003cp\u003e15.2 Wireless Interconnect Technologies 547\u003c\/p\u003e \u003cp\u003e15.2.1 Figure of Merit for Wireless Interconnects 547\u003c\/p\u003e \u003cp\u003e15.2.2 Capacitively Coupled Wireless Interconnects 549\u003c\/p\u003e \u003cp\u003e15.2.3 Inductively Coupled Wireless Interconnects 550\u003c\/p\u003e \u003cp\u003e15.2.4 Antennas and Propagation 553\u003c\/p\u003e \u003cp\u003e15.3 Conclusion 561\u003c\/p\u003e \u003cp\u003eReferences 561\u003c\/p\u003e \u003cp\u003e\u003cb\u003eIndex\u003c\/b\u003e\u003c\/p\u003e \u003cb\u003eMikhail R. Baklanov\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eIMEC, Leuven, Belgium\u003c\/i\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003ePaul S. Ho\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eLaboratory for Interconnect and Packaging, University of Texas at Austin, Austin, Texas, USA\u003c\/i\u003e\u003cbr\u003e\u003cbr\u003e\u003cb\u003eEhrenfried Zschech\u003c\/b\u003e\u003cbr\u003e\u003ci\u003eFraunhofer Institute for Nondestructive Testing, Dresden, Germany\u003c\/i\u003e  Finding new materials for copper\/low-k interconnects is critical to the continuing development of computer chips. While copper\/low-k interconnects have served well, allowing for the creation of Ultra Large Scale Integration (ULSI) devices which combine over a billion transistors onto a single chip, the increased resistance and RC-delay at the smaller scale has become a significant factor affecting chip performance.  \u003cp\u003e\u003ci\u003eAdvanced Interconnects for ULSI Technology\u003c\/i\u003e is dedicated to the materials and methods which might be suitable replacements. It covers a broad range of topics, from physical principles to design, fabrication, characterization, and application of new materials for nano-interconnects, and discusses:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eInterconnect functions, characterisations, electrical properties and wiring requirements\u003c\/li\u003e \u003cli\u003eLow-k materials: fundamentals, advances and mechanical  properties\u003c\/li\u003e \u003cli\u003eConductive layers and barriers\u003c\/li\u003e \u003cli\u003eIntegration and reliability including mechanical reliability, electromigration and electrical breakdown\u003c\/li\u003e \u003cli\u003eNew approaches including 3D, optical, wireless interchip, and carbon-based interconnects\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eIntended for postgraduate students and researchers, in academia and industry, this book provides a critical overview of the enabling technology at the heart of the future development of computer chips.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47988667547877,"sku":"NP9780470662540","price":245.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780470662540.jpg?v=1761781188","url":"https:\/\/k12savings.com\/products\/advanced-interconnects-for-ulsi-technology-isbn-9780470662540","provider":"K12savings","version":"1.0","type":"link"}