{"product_id":"vlsi-circuit-design-methodology-demystified-isbn-9780470127421","title":"VLSI Circuit Design Methodology Demystified","description":"This book was written to arm engineers qualified and knowledgeable in the area of VLSI circuits with the essential knowledge they need to get into this exciting field and to help those already in it achieve a higher level of proficiency. Few people truly understand how a large chip is developed, but an understanding of the whole process is necessary to appreciate the importance of each part of it and to understand the process from concept to silicon. It will teach readers how to become better engineers through a practical approach of diagnosing and attacking real-world problems. \u003cp\u003eForeword xi\u003cbr\u003e\u003ci\u003eRichard Templeton\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003eForeword xiii\u003cbr\u003e\u003ci\u003eHans Stork\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003ePreface xv\u003c\/p\u003e \u003cp\u003eAcknowledgments xvii\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 1 THE BIG PICTURE 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1. What is a chip? 1\u003c\/p\u003e \u003cp\u003e2. What are the requirements of a successful chip design? 3\u003c\/p\u003e \u003cp\u003e3. What are the challenges in today’s very deep submicron (VDSM), multimillion gate designs? 4\u003c\/p\u003e \u003cp\u003e4. What major process technologies are used in today’s design environment? 5\u003c\/p\u003e \u003cp\u003e5. What are the goals of new chip design? 8\u003c\/p\u003e \u003cp\u003e6. What are the major approaches of today’s very large scale integration (VLSI) circuit design practices? 9\u003c\/p\u003e \u003cp\u003e7. What is standard cell-based, application-specific integrated circuit (ASIC) design methodology? 11\u003c\/p\u003e \u003cp\u003e8. What is the system-on-chip (SoC) approach? 12\u003c\/p\u003e \u003cp\u003e9. What are the driving forces behind the SoC trend? 15\u003c\/p\u003e \u003cp\u003e10. What are the major tasks in developing a SoC chip from concept to silicon? 15\u003c\/p\u003e \u003cp\u003e11. What are the major costs of developing a chip? 16\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 2 THE BASICS OF THE CMOS PROCESS AND DEVICES 17\u003c\/b\u003e\u003cbr\u003e\u003cbr\u003e12. What are the major process steps in building MOSFET transistors? 17\u003c\/p\u003e \u003cp\u003e13. What are the two types of MOSFET transistors? 19\u003c\/p\u003e \u003cp\u003e14. What are base layers and metal layers? 20\u003c\/p\u003e \u003cp\u003e15. What are wafers and dies? 24\u003c\/p\u003e \u003cp\u003e16. What is semiconductor lithography? 28\u003c\/p\u003e \u003cp\u003e17. What is a package? 33\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 3 THE CHALLENGES IN VLSI CIRCUIT DESIGN 41\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e18. What is the role of functional verification in the IC design process? 41\u003cbr\u003e\u003cbr\u003e19. What are some of the design integrity issues? 44\u003c\/p\u003e \u003cp\u003e20. What is design for testability? 46\u003c\/p\u003e \u003cp\u003e21. Why is reducing the chip’s power consumption so important? 48\u003c\/p\u003e \u003cp\u003e22. What are some of the challenges in chip packaging? 49\u003c\/p\u003e \u003cp\u003e23. What are the advantages of design reuse? 50\u003c\/p\u003e \u003cp\u003e24. What is hardware\/software co-design? 51\u003c\/p\u003e \u003cp\u003e25. Why is the clock so important? 54\u003c\/p\u003e \u003cp\u003e26. What is the leakage current problem? 57\u003c\/p\u003e \u003cp\u003e27. What is design for manufacturability? 60\u003c\/p\u003e \u003cp\u003e28. What is chip reliability? 62\u003c\/p\u003e \u003cp\u003e29. What is analog integration in the digital environment? 65\u003c\/p\u003e \u003cp\u003e30. What is the role of EDA tools in IC design? 67\u003c\/p\u003e \u003cp\u003e31. What is the role of the embedded processor in the SoC environment? 69\u003c\/p\u003e \u003cp\u003e\u003cb\u003eCHAPTER 4 CELL-BASED ASIC DESIGN METHODOLOGY 73\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e32. What are the major tasks and personnel required in a chip design project? 73\u003c\/p\u003e \u003cp\u003e33. What are the major steps in ASIC chip construction? 74\u003c\/p\u003e \u003cp\u003e34. What is the ASIC design flow? 75\u003c\/p\u003e \u003cp\u003e35. What are the two major aspects of ASIC design flow? 77\u003c\/p\u003e \u003cp\u003e36. What are the characteristics of good design flow? 80\u003c\/p\u003e \u003cp\u003e37. What is the role of market research in an ASIC project? 81\u003c\/p\u003e \u003cp\u003e38. What is the optimal solution of an ASIC project? 82\u003c\/p\u003e \u003cp\u003e39. What is system-level study of a project? 84\u003c\/p\u003e \u003cp\u003e40. What are the approaches for verifying design at the system level? 85\u003c\/p\u003e \u003cp\u003e41. What is register-transfer-level (RTL) system-level description? 86\u003c\/p\u003e \u003cp\u003e42. What are methods of verifying design at the register-transfer-level? 87\u003c\/p\u003e \u003cp\u003e43. What is a test bench? 88\u003c\/p\u003e \u003cp\u003e44. What is code coverage? 89\u003c\/p\u003e \u003cp\u003e45. What is functional coverage? 89\u003c\/p\u003e \u003cp\u003e46. What is bug rate convergence? 90\u003c\/p\u003e \u003cp\u003e47. What is design planning? 91\u003c\/p\u003e \u003cp\u003e48. What are hard macro and soft macro? 92\u003c\/p\u003e \u003cp\u003e49. What is hardware description language (HDL)? 92\u003c\/p\u003e \u003cp\u003e50. What is register-transfer-level (RTL) description of hardware? 93\u003c\/p\u003e \u003cp\u003e51. What is standard cell? What are the differences among standard cell, gate-array, and sea-of-gate approaches? 94\u003c\/p\u003e \u003cp\u003e52. What is an ASIC library? 103\u003c\/p\u003e \u003cp\u003e53. What is logic synthesis? 105\u003c\/p\u003e \u003cp\u003e54. What are the optimization targets of logic synthesis? 106\u003c\/p\u003e \u003cp\u003e55. What is schematic or netlist? 107\u003c\/p\u003e \u003cp\u003e56. What is the gate count of a design? 111\u003c\/p\u003e \u003cp\u003e57. What is the purpose of test insertion during logic synthesis? 111\u003c\/p\u003e \u003cp\u003e58. What is the most commonly used model in VLSI circuit testing? 112\u003c\/p\u003e \u003cp\u003e59. What are controllability and observability in a digital circuit? 114\u003c\/p\u003e \u003cp\u003e60. What is a testable circuit? 115\u003c\/p\u003e \u003cp\u003e61. What is the aim of scan insertion? 116\u003c\/p\u003e \u003cp\u003e62. What is fault coverage? What is defect part per million (DPPM)? 117\u003c\/p\u003e \u003cp\u003e63. Why is design for testability important for a product’s financial success? 119\u003c\/p\u003e \u003cp\u003e64. What is chip power usage analysis? 120\u003c\/p\u003e \u003cp\u003e65. What are the major components of CMOS power consumption? 121\u003c\/p\u003e \u003cp\u003e66. What is power optimization? 123\u003c\/p\u003e \u003cp\u003e67. What is VLSI physical design? 123\u003c\/p\u003e \u003cp\u003e68. What are the problems that make VLSI physical design so challenging? 124\u003c\/p\u003e \u003cp\u003e69. What is floorplanning? 128\u003c\/p\u003e \u003cp\u003e70. What is the placement process? 131\u003c\/p\u003e \u003cp\u003e71. What is the routing process? 133\u003c\/p\u003e \u003cp\u003e72. What is a power network? 135\u003c\/p\u003e \u003cp\u003e73. What is clock distribution? 139\u003c\/p\u003e \u003cp\u003e74. What are the key requirements for constructing a clock tree? 143\u003c\/p\u003e \u003cp\u003e75. What is the difference between time skew and length skew in a clock tree? 145\u003c\/p\u003e \u003cp\u003e76. What is scan chain? 149\u003c\/p\u003e \u003cp\u003e77. What is scan chain reordering? 151\u003c\/p\u003e \u003cp\u003e78. What is parasitic extraction? 152\u003c\/p\u003e \u003cp\u003e79. What is delay calculation? 155\u003c\/p\u003e \u003cp\u003e80. What is back annotation? 156\u003c\/p\u003e \u003cp\u003e81. What kind of signal integrity problems do place and route tools handle? 156\u003c\/p\u003e \u003cp\u003e82. What is cross-talk delay? 157\u003c\/p\u003e \u003cp\u003e83. What is cross-talk noise? 158\u003c\/p\u003e \u003cp\u003e84. What is IR drop? 159\u003c\/p\u003e \u003cp\u003e85. What are the major netlist formats for design representation? 162\u003c\/p\u003e \u003cp\u003e86. What is gate-level logic verification before tapeout? 162\u003c\/p\u003e \u003cp\u003e87. What is equivalence check? 163\u003c\/p\u003e \u003cp\u003e88. What is timing verification? 164\u003c\/p\u003e \u003cp\u003e89. What is design constraint? 165\u003c\/p\u003e \u003cp\u003e90. What is static timing analysis (STA)? 165\u003c\/p\u003e \u003cp\u003e91. What is simulation approach on timing verification? 169\u003c\/p\u003e \u003cp\u003e92. What is the logical-effort-based timing closure approach? 173\u003c\/p\u003e \u003cp\u003e93. What is physical verification? 178\u003c\/p\u003e \u003cp\u003e94. What are design rule check (DRC), design verification (DV), and geometry verification (GV)? 179\u003c\/p\u003e \u003cp\u003e95. What is schematic verification (SV) or layout versus schematic (LVS)? 181\u003c\/p\u003e \u003cp\u003e96. What is automatic test pattern generation (ATPG)? 182\u003c\/p\u003e \u003cp\u003e97. What is tapeout? 184\u003c\/p\u003e \u003cp\u003e98. What is yield? 184\u003c\/p\u003e \u003cp\u003e99. What are the qualities of a good IC implementation designer? 187\u003c\/p\u003e \u003cp\u003eConclusion 189\u003c\/p\u003e \u003cp\u003eAcronyms 191\u003c\/p\u003e \u003cp\u003eBibliography 195\u003c\/p\u003e \u003cp\u003eIndex 199\u003c\/p\u003e \u003cp\u003eLiming Xiu is a Design Engineer and a Senior Member of Technical Staff (SMTS) at Texas Instruments, Inc. His interests include digital and mixed-signal integrated circuit design and VLSI physical design. He has worked on various mixed-signal devices, including video decoders, 3-D graphics controllers, and HDTV decoders, as physical design lead. He is also a Phase Lock Loop (PLL) expert. He is the inventor of \"Flying-Adder\" frequency and phase synthesis architecture, which has been used in many commercial products. He has eleven granted or pending U.S. patents. He is a Senior Member of the IEEE and the general chair of the IEEE Circuit and Systems Society, Dallas Chapter.\u003c\/p\u003e   \u003cp\u003eAn accessible, intuitive resource to common—and not-so-common—questions and answers about very large-scale integrated (VLSI) circuit design\u003c\/p\u003e \u003cp\u003eThe widespread acceptance of sophisticated electronic devices and the growing challenges of a more technically oriented future have created an unprecedented demand for very large-scale integrated (VLSI) circuits. Meeting this crucial need requires advances in material science and processing equipment along with the ability to use the computer more effectively to aid in the design process. More importantly, it also requires a significant number of qualified professionals to work in this exciting field. Unfortunately, due to its complexity and dynamic nature, the topic of VLSI circuit design methodology is not widely taught in universities nor is it well understood by many engineers. Now, VLSI Circuit Design Methodology Demystified takes the guesswork out of this important topic by presenting readers with a succinct and accessible treatment of how a complex chip is developed, from concept to silicon.\u003c\/p\u003e \u003cp\u003eUniquely organized in a question-and-answer format, the book builds on information in the order of chip development: market research\/product definition, system design, logic design, logic verification, logic synthesis, Place \u0026amp; Route, and physical verification. A wealth of important questions are addressed, including:\u003c\/p\u003e \u003cul\u003e \u003cli\u003e \u003cp\u003eWhat are the requirements of a successful chip design?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat are the major approaches of today's VLSI circuit design practices?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat are the major process steps in building MOSFET transistors?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat is the role of functional verification in the IC design process?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat are the two major aspects of ASIC design flow?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat is Hardware Description Language (HDL)?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat is the most commonly used model in VLSI circuit testing?\u003c\/p\u003e \u003c\/li\u003e \u003cli\u003e \u003cp\u003eWhat are the qualities of a good IC implementation designer?\u003c\/p\u003e \u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eThe answers to these questions and many more provide the framework for understanding the key concepts involved in the VLSI chip development process, giving readers a solid foundation for further advancement in the field. Written by an industry expert, the book uses up-to-date, real-world design examples to demonstrate to readers how to become better engineers through a practical approach of diagnosing and attacking problems. Ideal as a resource for electrical engineers specializing in integrated circuit design in the semiconductor industry, this book is also suitable as a supplementary text for students enrolled in advanced VLSI courses.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47990460580069,"sku":"NP9780470127421","price":112.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780470127421.jpg?v=1761787917","url":"https:\/\/k12savings.com\/es\/products\/vlsi-circuit-design-methodology-demystified-isbn-9780470127421","provider":"K12savings","version":"1.0","type":"link"}