{"product_id":"phase-locking-in-high-performance-systems-isbn-9780471447276","title":"Phase-Locking in High-Performance Systems","description":"Comprehensive coverage of recent developments in phase-locked loop technology\u003cbr\u003e \u003cbr\u003e The rapid growth of high-speed semiconductor and communication technologies has helped make phase-locked loops (PLLs) an essential part of memories, microprocessors, radio-frequency (RF) transceivers, broadband data communication systems, and other burgeoning fields. Complementing his 1996 Monolithic Phase-Locked Loops and Clock Recovery Circuits (Wiley-IEEE Press), Behzad Razavi now has collected the most important recent writing on PLL into a comprehensive, self-contained look at PLL devices, circuits, and architectures.\u003cbr\u003e \u003cbr\u003e Phase-Locking in High-Performance Systems: From Devices to Architectures' five original tutorials and eighty-three key papers provide an eminently readable foundation in phase-locked systems. Analog and digital circuit designers will glean a wide range of practical information from the book's . . .\u003cbr\u003e * Tutorials dealing with devices, delay-locked loops (DLLs), fractional-N synthesizers, bang-bang PLLs, and simulation of phase noise and jitter\u003cbr\u003e * In-depth discussions of passive devices such as inductors, transformers, and varactors\u003cbr\u003e * Papers on the analysis of phase noise and jitter in various types of oscillators\u003cbr\u003e * Concentrated examinations of building blocks, including the design of oscillators, frequency dividers, and phase\/frequency detectors\u003cbr\u003e * Articles addressing the problem of clock generation by phase-locking for timing and digital applications, RF synthesis, and the application of phase-locking to clock and data recovery circuits\u003cbr\u003e \u003cbr\u003e In tandem with its companion volume, Phase-Locking in High-Performance Systems: From Devices to Architectures is a superb reference for anyone working on, or seeking to better understand, this rapidly-developing and increasingly central technology.  Preface.  \u003cp\u003eAbout the Author.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart I: Original Contributions.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eDevices and Circuits for Phase-Locked Systems.\u003c\/p\u003e \u003cp\u003eDelay-Locked Loops - An Overview.\u003c\/p\u003e \u003cp\u003eDelta-Sigma Fractional-N Phase-Locked Loops.\u003c\/p\u003e \u003cp\u003eDesign Bang-Bang PLLs for Clock and Data Recovery in Serial Data Transmission Systems.\u003c\/p\u003e \u003cp\u003ePredicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart II: Devices.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003ePhysics-Based Closed-Form Inductance Expression for Compact Modeling of Integrated Spiral Inductors.\u003c\/p\u003e \u003cp\u003eThe Modeling, Characterization, and Design of Monolithic Inductors for Silicon RF IC's.\u003c\/p\u003e \u003cp\u003eAnalysis, Design, and Optimization of Spiral Inductors and Transformers for Si RF IC's.\u003c\/p\u003e \u003cp\u003eStacked Inductors and Transformers in CMOS Technology.\u003c\/p\u003e \u003cp\u003eEstimation Methods for Quality Factors of Inductors Fabricated in Silicon Integrated Circuit Process Technologies.\u003c\/p\u003e \u003cp\u003eA Q-Factor Enhancement Technique for MMIC Inductors.\u003c\/p\u003e \u003cp\u003eOn-Chip Spiral Inductors with Patterned Ground Shields for Si-Based RF IC's.\u003c\/p\u003e \u003cp\u003eThe Effects of a Ground Shield on the Characteristics and Performance of Spiral Inductors.\u003c\/p\u003e \u003cp\u003eTemperature Dependence of Q and Inductance in Spiral Inductors Fabricated in a Silicon-Germanium\/BiCMOS Technology.\u003c\/p\u003e \u003cp\u003eSubstrate Noise Coupling Through Planar Spiral Inductor.\u003c\/p\u003e \u003cp\u003eDesign of High-Q Varactors for Low-Power Wireless Applications Using a Standard CMOS Process.\u003c\/p\u003e \u003cp\u003eOn the Use of MOS Varactors in RF VCO's.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart III: Phase Noise and Jitter.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eLow-Noise Voltage-Controlled Oscillators Using Enhanced LC-Tanks.\u003c\/p\u003e \u003cp\u003eA Study of Phase Noise in CMOS Oscillators.\u003c\/p\u003e \u003cp\u003eA General Theory of Phase Noise in Electrical Oscillators.\u003c\/p\u003e \u003cp\u003ePhysical Processes of Phase Noise in Differential LC Oscillators.\u003c\/p\u003e \u003cp\u003ePhase Noise in LC Oscillators.\u003c\/p\u003e \u003cp\u003eThe Effect of Varactor Nonlinearity on the Phase Noise of Completely Integrated VCOs.\u003c\/p\u003e \u003cp\u003eJitter in Ring Oscillators.\u003c\/p\u003e \u003cp\u003eJitter and Phase Noise in Ring Oscillators.\u003c\/p\u003e \u003cp\u003eA Study of Oscillator Jitter Due to Supply and Substrate Noise.\u003c\/p\u003e \u003cp\u003eMeasurements and Analysis of PLL Jitter Caused by Digital Switching Noise.\u003c\/p\u003e \u003cp\u003eOn-Chip Measurement of the Jitter Transfer Function of Charge-Pump Phase-Locked Loops.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart IV: Building Blocks.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA Low-Noise, Low-Power VCO with Automatic Amplitude Control for Wireless Applications.\u003c\/p\u003e \u003cp\u003eA Fully Integrated VCO at 2 GHz.\u003c\/p\u003e \u003cp\u003eTail Current Noise Suppression in RF CMOS VCOs.\u003c\/p\u003e \u003cp\u003eLow-Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS.\u003c\/p\u003e \u003cp\u003eAnalysis and Design of an Optimally Coupled 5-GHz Quadrature LC Oscillator.\u003c\/p\u003e \u003cp\u003eA 1.57-GHz Fully Integrated Very Low-Phase-Noise Quadrature VCO.\u003c\/p\u003e \u003cp\u003eA Low-Phase-Noise 5GHz Quadrature CMOS VCO Using Common-Mode Inductive Coupling.\u003c\/p\u003e \u003cp\u003eAn Integrated 10\/5GHz Injection-Locked Quadrature LC VCO in a 0.18[mu]m Digital CMOS Process.\u003c\/p\u003e \u003cp\u003eRotary Traveling-Wave Oscillator Arrays: A New Clock Technology.\u003c\/p\u003e \u003cp\u003e35-GHz Static and 48-GHz Dynamic Frequency Divider IC's Using 0.2-[mu]m AlGaAs\/GaAs-HEMT's.\u003c\/p\u003e \u003cp\u003eSuperharmonic Injection-Locked Frequency Dividers.\u003c\/p\u003e \u003cp\u003eA Family of Low-Power Truly Modular Programmable Dividers in Standard 0.35-[mu]m CMOS Technology.\u003c\/p\u003e \u003cp\u003eA 1.75-GHz\/3-V Dual-Modulus Divide-by-128\/129 Prescaler in 0.7-[mu]m CMOS.\u003c\/p\u003e \u003cp\u003eA 1.2 GHz CMOS Dual-Modulus Prescaler Using New Dynamic D-Type Flip-Flops.\u003c\/p\u003e \u003cp\u003eHigh-Speed Architecture for a Programmable Frequency Divider and a Dual-Modulus Prescaler.\u003c\/p\u003e \u003cp\u003eA 1.6-GHz Dual Modulus Prescaler Using the Extended True-Single-Phase-Clock CMOS Circuit Technique (E-TSPC).\u003c\/p\u003e \u003cp\u003eA Simple Precharged CMOS Phase Frequency Detector.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart V: Clock Generation by PLLs and DLLs.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for Microprocessor Clock Generation.\u003c\/p\u003e \u003cp\u003eA Low Jitter 0.3-165 MHz CMOS PLL Frequency Synthesizer for 3 V\/5 V Operation.\u003c\/p\u003e \u003cp\u003eLow-Jitter Process-Independent DLL and PLL Based on Self-Biased Techniques.\u003c\/p\u003e \u003cp\u003eA Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340-612 MHz.\u003c\/p\u003e \u003cp\u003eA 960-Mb\/s\/pin Interface for Skew-Tolerant Bus Using Low Jitter PLL.\u003c\/p\u003e \u003cp\u003eActive GHz Clock Network Using Distributed PLLs.\u003c\/p\u003e \u003cp\u003eA Low-Noise Fast-Lock Phase-Locked Loop with Adaptive Bandwidth Control.\u003c\/p\u003e \u003cp\u003eA Low-Jitter 125-1250-MHz Process-Independent and Ripple-Poleless 0.18-[mu]m CMOS PLL Based on a Sample-Reset Loop Filter.\u003c\/p\u003e \u003cp\u003eA Dual-Loop Delay-Locked Loop Using Multiple Voltage-Controlled Delay Lines.\u003c\/p\u003e \u003cp\u003eAn All-Analog Multiphase Delay-Locked Loop Using a Replica Delay Line for Wide-Range Operation and Low-Jitter Performance.\u003c\/p\u003e \u003cp\u003eA Semidigital Dual Delay-Locked Loop.\u003c\/p\u003e \u003cp\u003eA Wide-Range Delay-Locked Loop with a Fixed Latency of One Clock Cycle.\u003c\/p\u003e \u003cp\u003eA Portable Digital DLL for High-Speed CMOS Interface Circuits.\u003c\/p\u003e \u003cp\u003eCMOS DLL-Base 2-V 3.2-ps Jitter 1-GHz Clock Synthesizer and Temperature-Compensated Tunable Oscillator.\u003c\/p\u003e \u003cp\u003eA 1.5V 86 mW\/ch 8-Channel 622-3125-Mb\/s\/ch CMOS SerDes Macrocell with Selectable Mux\/Demux Ratio.\u003c\/p\u003e \u003cp\u003eA Register-Controlled Symmetrical DLL for Double-Data-Rate DRAM.\u003c\/p\u003e \u003cp\u003eA Low-Jitter Wide-Range Skew-Calibrated Dual-Loop DLL Using Antifuse Circuitry for High-Speed DRAM.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart VI: RF Synthesis.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eAn Adaptive PLL Tuning System Architecture Combining High Spectral Purity and Fast Settling Time.\u003c\/p\u003e \u003cp\u003eA 2-V 900-MHz Monolithic CMOS Dual-Loop Frequency Synthesizer for GSM Receivers.\u003c\/p\u003e \u003cp\u003eA CMOS Frequency Synthesizer with an Injection-Locked Frequency Divider for a 5-GHz Wireless LAN Receiver.\u003c\/p\u003e \u003cp\u003eA 2.6-GHz\/5.2-GHz Frequency Synthesizer in 0.4-[mu]m CMOS Technology.\u003c\/p\u003e \u003cp\u003eFast Switching Frequency Synthesizer with a Discriminator-Aided Phase Detector.\u003c\/p\u003e \u003cp\u003eLow-Power Dividerless Frequency Synthesis Using Aperture Phase Detection.\u003c\/p\u003e \u003cp\u003eA Stabilization Technique for Phase-Locked Frequency Synthesizers.\u003c\/p\u003e \u003cp\u003eA Modeling Approach for [Sigma]-[Delta] Fractional-N Frequency Synthesizers Allowing Straightforward Noise Analysis.\u003c\/p\u003e \u003cp\u003eA Fully Integrated CMOS Frequency Synthesizer with Charge-Averaging Charge Pump and Dual-Path Loop Filter for PCS- and Cellular-CDMA Wireless Systems.\u003c\/p\u003e \u003cp\u003eA 1.1-GHz CMOS Fraction-N Frequency Synthesizer With a 3-b Third-Order [Sigma]-[Delta] Modulator.\u003c\/p\u003e \u003cp\u003eA 1.8-GHz Self-Calibrated Phase-Locked Loop with Precise I\/Q Matching.\u003c\/p\u003e \u003cp\u003eA 27-mW CMOS Fractional-N Synthesizer Using Digital Compensation for 2.5-Mb\/s GFSK Modulation.\u003c\/p\u003e \u003cp\u003eA CMOS Monolothic [Sigma][Delta]-Controlled Fractional-N Frequency Synthesizer for DSC-1800.\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart VII: Clock and Data Recovery.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eA 2.5-Gb\/s Clock and Data Recovery IC with Tunable Jitter Characteristics for Use in LAN's and WAN's.\u003c\/p\u003e \u003cp\u003eClock\/Data Recovery PLL Using Half-Frequency Clock.\u003c\/p\u003e \u003cp\u003eA 0.5-[mu]m CMOS 4.0-Gbit\/s Serial Link Transceiver with Data Recovery Using Oversampling.\u003c\/p\u003e \u003cp\u003eA 2-1600-MHz CMOS Clock Recovery PLL with Low-Vdd Capability.\u003c\/p\u003e \u003cp\u003eSiGe Clock and Data Recovery IC with Linear-Type PLL for 10-Gb\/s SONET Application.\u003c\/p\u003e \u003cp\u003eA Fully Integrated SiGe Receiver IC for 10-Gb\/s Data Rate.\u003c\/p\u003e \u003cp\u003eA 10-Gb\/s CMOS Clock and Data Recovery Circuit with a Half-Rate Linear Phase Detector.\u003c\/p\u003e \u003cp\u003eA 10-Gb\/s CMOS Clock and Data Recovery Circuit with Frequency Detection.\u003c\/p\u003e \u003cp\u003eA 10-Gb\/s CDR\/DEMUX with LC Delay Line VCO in 0.18[mu]m CMOS.\u003c\/p\u003e \u003cp\u003eA 40-Gb\/s Integrated Clock and Data Recovery Circuit in a 50-GHz f[subscript T] Silicon Bipolar Technology.\u003c\/p\u003e \u003cp\u003eA Fully Integrated 40-Gb\/s Clock and Data Recovery IC With 1:4 DEMUX in SiGe Technology.\u003c\/p\u003e \u003cp\u003eClock and Data Recovery IC for 40-Gb\/s Fiber-Optic Receiver.\u003c\/p\u003e \u003cp\u003eIndex.\u003c\/p\u003e BEHZAD RAZAVI, is Professor of Electrical Engineering at UCLA, where he conducts research on wireless transceivers, broadband data communications, and phenomena related to phase-locking. He is a Fellow of IEEE and an IEEE Distinguished Lecturer. He is the author of Principles of Data Conversion System Design, RF Microelectronics, and Design of Analog CMOS Integrated Circuits, and the editor of Monolithic Phase-Locked Loops and Clock Recovery Circuits   Comprehensive coverage of recent developments in phase-locked loop technology  \u003cp\u003eThe rapid growth of high-speed semiconductor and communication technologies has helped make phase-locked loops (PLLs) an essential part of memories, microprocessors, radio-frequency (RF) transceivers, broadband data communication systems, and other burgeoning fields. Complementing his 1996 Monolithic Phase-Locked Loops and Clock Recovery Circuits (Wiley-IEEE Press), Behzad Razavi now has collected the most important recent writing on PLL into a comprehensive, self-contained look at PLL devices, circuits, and architectures.\u003c\/p\u003e \u003cp\u003ePhase-Locking in High-Performance Systems: From Devices to Architectures’ five original tutorials and eighty-three key papers provide an eminently readable foundation in phase-locked systems. Analog and digital circuit designers will glean a wide range of practical information from the book’s . . .\u003c\/p\u003e \u003cul\u003e \u003cli\u003eTutorials dealing with devices, delay-locked loops (DLLs), fractional-N synthesizers, bang-bang PLLs, and simulation of phase noise and jitter\u003c\/li\u003e \u003cli\u003eIn-depth discussions of passive devices such as inductors, transformers, and varactors\u003c\/li\u003e \u003cli\u003ePapers on the analysis of phase noise and jitter in various types of oscillators\u003c\/li\u003e \u003cli\u003eConcentrated examinations of building blocks, including the design of oscillators, frequency dividers, and phase\/frequency detectors\u003c\/li\u003e \u003cli\u003eArticles addressing the problem of clock generation by phase-locking for timing and digital applications, RF synthesis, and the application of phase-locking to clock and data recovery circuits\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eIn tandem with its companion volume, Phase-Locking in High-Performance Systems: From Devices to Architectures is a superb reference for anyone working on, or seeking to better understand, this rapidly-developing and increasingly central technology.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989773926629,"sku":"NP9780471447276","price":234.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780471447276.jpg?v=1761785427","url":"https:\/\/k12savings.com\/es\/products\/phase-locking-in-high-performance-systems-isbn-9780471447276","provider":"K12savings","version":"1.0","type":"link"}