{"product_id":"monolithic-phase-locked-loops-and-clock-recovery-circuits-isbn-9780780311497","title":"Monolithic Phase-Locked Loops and Clock Recovery Circuits","description":"Featuring an extensive 40 page tutorial introduction, this carefully compiled anthology of 65 of the most important papers on phase-locked loops and clock recovery circuits brings you comprehensive coverage of the field-all in one self-contained volume. You'll gain an understanding of the analysis, design, simulation, and implementation of phase-locked loops and clock recovery circuits in CMOS and bipolar technologies along with valuable insights into the issues and trade-offs associated with phase locked systems for high speed, low power, and low noise.  Preface.  \u003cp\u003eDesign of Monolithic Phase-Locked Loops and Clock Recovery Circuits—A Tutorial (B. Razavi).\u003c\/p\u003e \u003cp\u003eBASIC THEORY.\u003c\/p\u003e \u003cp\u003eTheory of AFC Synchronization (W. Gruen).\u003c\/p\u003e \u003cp\u003eColor-Carrier Reference Phase Synchronization Accuracy in NTSC Color Television (D. Richman).\u003c\/p\u003e \u003cp\u003eCharge-Pump Phase-Locked Loops (F. Gardner).\u003c\/p\u003e \u003cp\u003ez-Domain Model for Discrete-Time PLLs (J. Hein \u0026amp; J. Scott).\u003c\/p\u003e \u003cp\u003eAnalyze PLLs with Discrete Time Modeling (J. Kovacs).\u003c\/p\u003e \u003cp\u003eProperties of Frequency Difference Detectors (F. Gardner).\u003c\/p\u003e \u003cp\u003eFrequency Detectors for PLL Acquisition in Timing and Carrier Recovery (D. Messerschmitt).\u003c\/p\u003e \u003cp\u003eAnalysis of Phase-Locked Timing Extraction Circuits for Pulse Code Transmission (E. Roza).\u003c\/p\u003e \u003cp\u003eOptimization of Phase-Locked Loop Performance in Data Recovery Systems (R. Co \u0026amp; J. Mulligan).\u003c\/p\u003e \u003cp\u003eNoise Properties of PLL Systems (V. Kroupa).\u003c\/p\u003e \u003cp\u003ePLL\/DLL System Noise Analysis for Low Jitter Clock Synthesizer Design (B. Kim, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003ePractical Approach Augurs PLL Noise in RF Synthesizers (M. O'Leary).\u003c\/p\u003e \u003cp\u003eThe Effects of Noise in Oscillators (E. Hafner).\u003c\/p\u003e \u003cp\u003eA Simple Model of Feedback Oscillator Noise Spectrum (D. Leeson).\u003c\/p\u003e \u003cp\u003eNoise in Relaxation Oscillators (A. Abidi \u0026amp; R. Meyer).\u003c\/p\u003e \u003cp\u003eAnalysis of Timing Jitter in CMOS Ring Oscillators (T. Weigandt, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eAnalysis, Modeling, and Simulation of Phase Noise in Monolithic Voltage-Controlled Oscillators (B. Razavi).\u003c\/p\u003e \u003cp\u003eBUILDING BLOCKS.\u003c\/p\u003e \u003cp\u003eStart-up and Frequency Stability in High-Frequency Oscillators (N. Nguyen \u0026amp; R. Meyer).\u003c\/p\u003e \u003cp\u003eMOS Oscillators with Multi-Decade Tuning Range and Gigahertz Maximum Speed (M. Banu).\u003c\/p\u003e \u003cp\u003eA Bipolar 1 GHz Multi-Decade Monolithic Variable-Frequency Oscillator (J. Wu).\u003c\/p\u003e \u003cp\u003eA Digital Phase and Frequency Sensitive Detector (J. Brown).\u003c\/p\u003e \u003cp\u003eA 3-State Phase Detector Can Improve Your Next PLL Design (C. Sharpe).\u003c\/p\u003e \u003cp\u003eGaAs Monolithic Phase\/Frequency Discriminator (I. Shahriary, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eA New Phase-Locked Loop Timing Recovery Method for Digital Regenerators (J. Bellisio).\u003c\/p\u003e \u003cp\u003eA Phase-Locked Loop with Digital Frequency Comparator for Timing Signal Recovery (J. Afonso, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eClock Recovery from Random Binary Signals (J. Alexander).\u003c\/p\u003e \u003cp\u003eA Si Bipolar Phase and Frequency Detector IC for Clock Extraction up to 8 Gb\/s (A. Pottbacker, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Self-Correcting Clock Recovery Circuit (C. Hogge).\u003c\/p\u003e \u003cp\u003eMODELING AND SIMULATION.\u003c\/p\u003e \u003cp\u003eAn Integrated PLL Clock Generator for 275 MHz Graphic Displays (G. Gutierrez \u0026amp; D. DeSimone).\u003c\/p\u003e \u003cp\u003eThe Macro Modeling of Phase-Locked Loopes for the SPICE Simulator (M. Sitkowski).\u003c\/p\u003e \u003cp\u003eModeling and Simulation of an Analog Charge Pump Phase-Locked Loop (S. Can \u0026amp; Y. Sahinkaya).\u003c\/p\u003e \u003cp\u003eMixed-Mode Simulation of Phase-Locked Loops (B. Antao, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eBehavioral Representation for VCO and Detectors in Phase-Lock Systems (E. Liu \u0026amp; A. Sangiovanni-Vincentelli).\u003c\/p\u003e \u003cp\u003eBehavioral Simulation Techniques for Phase\/Delay-Locked Systems (A. Demir, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003ePHASE-LOCKED LOOPS.\u003c\/p\u003e \u003cp\u003eA Monolithic Phase-Locked Loop with Detection Processor (E. Murthi).\u003c\/p\u003e \u003cp\u003eA 200-MHz CMOS Phase-Locked Loop with Dual Phase Detectors (K. Ware, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eHigh-Frequency Phase-Locked Loops in Monolithic Bipolar Technology (M. Soyuer \u0026amp; R. Meyer).\u003c\/p\u003e \u003cp\u003eA 6-GHz Integrated Phase-Locked Loop Using AlGaAs\/GaAs Heterojunction Bipolar Transistors (A. Buchwald, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eA 6-GHz 60-mW BiCMOS Phase-Locked Loop with 2-V Supply (B. Razavi \u0026amp; J. Sung).\u003c\/p\u003e \u003cp\u003eDesign of PLL-Based Clock Generation Circuits (D. Jeong).\u003c\/p\u003e \u003cp\u003eA Variable Delay Line PLL for CPU-Coprocessor Synchronization (M. Johnson \u0026amp; E. Hudson).\u003c\/p\u003e \u003cp\u003eA PLL Clock Generator with 5 to 110 MHz of Lock Range for Microprocessors (I. Young, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA Wide-Bandwidth Low-Voltage PLL for PowerPC Microprocessors (J. Alvarez, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eA 30-128 MHz Frequency Synthesizer Standard Cell (R. Bitting \u0026amp; W. Repasky).\u003c\/p\u003e \u003cp\u003eCell-Based Fully Integrated CMOS Frequency Synthesizers (D. Mijuskovic, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eFully-Integrated CMOS Phase-Locked Loop with 15 to 240 MHz Locking Range and ±50 psec Jitter (I. Novof, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003ePLL Design for a 500 MB\/s Interface (M. Horowitz, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eCLOCK AND DATA RECOVERY CIRCUITS.\u003c\/p\u003e \u003cp\u003eAn Analog PLL-Based Clock and Data Recovery Circuit with High Input Jitter Tolerance (S. Sun).\u003c\/p\u003e \u003cp\u003eA 30-MHz Hybrid Analog\/Digital Clock Recovery Circuit in 2-μm CMOS (B. Kim, \u003ci\u003eet al.\u003c\/i\u003e).\u003c\/p\u003e \u003cp\u003eA BiCMOS PLL-Based Data Separator Circuit with High Stability and Accuracy (S. Miyazawa, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eA Versatile Clock Recovery Architecture and Monlithic Implementation (L. De Vito).\u003c\/p\u003e \u003cp\u003eA 155-MHz Clock Recovery Delay- and Phase-Locked Loop (T. Lee \u0026amp; J. Bulzacchelli).\u003c\/p\u003e \u003cp\u003eA Monolithic 156 Mb\/s Clock and Data Recovery PLL Circuit using the Sample- and-Hold Technique (N. Ishihara \u0026amp; Y. Akazawa).\u003c\/p\u003e \u003cp\u003eA Monolithic 480 Mb\/s Parallel AGC\/Decision\/Clock Recovery Circuit in 1.2-μm CMOS (T. Hu \u0026amp; P. Gray).\u003c\/p\u003e \u003cp\u003eA Monolithic 622 Mb\/sec Clock Extraction and Data Retiming Circuit (B. Lai \u0026amp; R. Walker).\u003c\/p\u003e \u003cp\u003eA 660 Mb\/s CMOS Clock Recovery Circuit with Instantaneous Locking for NRZ Data and Burst-Mode Transmission (M. Banu \u0026amp; A. Dunlop).\u003c\/p\u003e \u003cp\u003eA Monolithic 2.3-Gb\/s 100-mW Clock and Data Recovery Circuit in Silicon Bipolar Technology (M. Soyuer).\u003c\/p\u003e \u003cp\u003eA 50 MHz Phase- and Frequency-Locked Loop (R. Cordell, \u003ci\u003eet al\u003c\/i\u003e.).\u003c\/p\u003e \u003cp\u003eNMOS ICs for Clock and Data Regeneration in Gigabit-per-Second Optical-Fiber Receivers (S. Enam \u0026amp; A. Abidi).\u003c\/p\u003e \u003cp\u003eA PLL-Based 2.5-Gb\/s Clock and Data Regenerator IC (H. Ransijn \u0026amp; P. O'Connor).\u003c\/p\u003e \u003cp\u003eA 2.5-Gb\/sec 15-mW BiCMOS Clock Recovery Circuit (B. Razavi \u0026amp; J. Sung).\u003c\/p\u003e \u003cp\u003eAn 8 GHz Silicon Bipolar Clock Recovery and Data Regenerator IC (A. Pottbacker \u0026amp; U. Langmann).\u003c\/p\u003e \u003cp\u003eAuthor Index.\u003c\/p\u003e \u003cp\u003eSubject Index.\u003c\/p\u003e \u003cp\u003eEditor's Biography.\u003c\/p\u003e  \u003cp\u003e\u003cstrong\u003eBEHZAD RAZAVI, PhD,\u003c\/strong\u003e Professor of Electrical Enginnering at University of California, Los Angeles, is an award-winning author, researcher, and teacher. His research deals with wireless and wireline transceivers, high-speed communication circuits, and data converters. Author of more than 100 papers and seven popular books, Prof. Razavi is a Fellow of the IEEE, has served as an IEEE Distinguished Lecturer, and was recognized as one of the top ten authors in the fifty-year history of the International Solid-State Circuits Conference. He received the IEEE Donald O. Pederson Award in 2012 for his pioneering contributions to the design of high-speed CMOS communication circuits.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989652881637,"sku":"NP9780780311497","price":250.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780780311497.jpg?v=1761784968","url":"https:\/\/k12savings.com\/es\/products\/monolithic-phase-locked-loops-and-clock-recovery-circuits-isbn-9780780311497","provider":"K12savings","version":"1.0","type":"link"}