{"product_id":"esd-testing-isbn-9780470511916","title":"ESD Testing","description":"\u003cp\u003eWith the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eESD Testing: From Components to Systems\u003c\/i\u003e updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup. \u003c\/p\u003e \u003cp\u003eKey features:\u003c\/p\u003e \u003cul\u003e \u003cli\u003eProvides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.\u003c\/li\u003e \u003cli\u003eDiscusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).\u003c\/li\u003e \u003cli\u003eDescribes both conventional testing and new testing techniques for both chip and system level evaluation.\u003c\/li\u003e \u003cli\u003eAddresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.\u003c\/li\u003e \u003cli\u003eDiscusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing. \u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eESD Testing: From Components to Systems\u003c\/i\u003e is part of the authors’ series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference.  In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.\u003c\/p\u003e \u003cp\u003eAbout the Author xvii\u003c\/p\u003e \u003cp\u003ePreface xix\u003c\/p\u003e \u003cp\u003eAcknowledgments xxiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Testing for ESD, EMI, EOS, EMC, and Latchup 1\u003c\/p\u003e \u003cp\u003e1.2 Component and System Level Testing 1\u003c\/p\u003e \u003cp\u003e1.3 Qualification Testing 2\u003c\/p\u003e \u003cp\u003e1.4 ESD Standards 3\u003c\/p\u003e \u003cp\u003e1.4.1 Standard Development – Standard Practice (SP) and Standard Test Methods (STMs) 3\u003c\/p\u003e \u003cp\u003e1.4.2 Repeatability 4\u003c\/p\u003e \u003cp\u003e1.4.3 Reproducibility 4\u003c\/p\u003e \u003cp\u003e1.4.4 Round Robin Testing 4\u003c\/p\u003e \u003cp\u003e1.4.5 Round Robin Statistical Analysis – k-Statistics 5\u003c\/p\u003e \u003cp\u003e1.4.6 Round Robin Statistical Analysis – h-Statistics 6\u003c\/p\u003e \u003cp\u003e1.5 Component Level Standards 6\u003c\/p\u003e \u003cp\u003e1.6 System Level Standards 7\u003c\/p\u003e \u003cp\u003e1.7 Factory and Material Standards 7\u003c\/p\u003e \u003cp\u003e1.8 Characterization Testing 8\u003c\/p\u003e \u003cp\u003e1.8.1 Semiconductor Component Level Characterization 9\u003c\/p\u003e \u003cp\u003e1.8.2 Semiconductor Device Level Characterization 9\u003c\/p\u003e \u003cp\u003e1.8.3 Wafer Level ESD Characterization Testing 9\u003c\/p\u003e \u003cp\u003e1.8.4 Device Characterization Tests on Circuits 10\u003c\/p\u003e \u003cp\u003e1.8.5 Device Characterization Tests on Components 10\u003c\/p\u003e \u003cp\u003e1.8.6 System level Characterization on Components 11\u003c\/p\u003e \u003cp\u003e1.8.7 Testing to Standard Specification Levels 11\u003c\/p\u003e \u003cp\u003e1.8.8 Testing to Failure 11\u003c\/p\u003e \u003cp\u003e1.9 ESD Library Characterization and Qualification 12\u003c\/p\u003e \u003cp\u003e1.10 ESD Component Standards and Chip Architectures 12\u003c\/p\u003e \u003cp\u003e1.10.1 Relationship Between ESD Standard Pin Combinations and Failure Mechanisms 12\u003c\/p\u003e \u003cp\u003e1.10.2 Relationship Between ESD Standard Pin Combinations and Chip Architecture 13\u003c\/p\u003e \u003cp\u003e1.11 System Level Characterization 13\u003c\/p\u003e \u003cp\u003e1.12 Summary and Closing Comments 13\u003c\/p\u003e \u003cp\u003eProblems 14\u003c\/p\u003e \u003cp\u003eReferences 15\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Human Body Model 17\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 History 17\u003c\/p\u003e \u003cp\u003e2.2 Scope 18\u003c\/p\u003e \u003cp\u003e2.3 Purpose 18\u003c\/p\u003e \u003cp\u003e2.4 Pulse Waveform 18\u003c\/p\u003e \u003cp\u003e2.5 Equivalent Circuit 19\u003c\/p\u003e \u003cp\u003e2.6 Test Equipment 20\u003c\/p\u003e \u003cp\u003e2.7 Test Sequence and Procedure 23\u003c\/p\u003e \u003cp\u003e2.8 Failure Mechanisms 25\u003c\/p\u003e \u003cp\u003e2.9 HBM ESD Current Paths 26\u003c\/p\u003e \u003cp\u003e2.10 HBM ESD Protection Circuit Solutions 28\u003c\/p\u003e \u003cp\u003e2.11 Alternate Test Methods 32\u003c\/p\u003e \u003cp\u003e2.11.1 HBM Split Fixture Testing 32\u003c\/p\u003e \u003cp\u003e2.11.2 HBM Sample Testing 33\u003c\/p\u003e \u003cp\u003e2.11.3 HBM Wafer Level ESD Testing 33\u003c\/p\u003e \u003cp\u003e2.11.4 HBM Test Extraction Across the Device Under Test (DUT) 33\u003c\/p\u003e \u003cp\u003e2.12 HBM Two-Pin Stress 34\u003c\/p\u003e \u003cp\u003e2.12.1 HBM Two-Pin Stress – Advantages 37\u003c\/p\u003e \u003cp\u003e2.12.2 HBM Two-Pin Stress – Pin Combinations 37\u003c\/p\u003e \u003cp\u003e2.13 HBM Small Step Stress 37\u003c\/p\u003e \u003cp\u003e2.13.1 HBM Small Step Stress – Advantages 38\u003c\/p\u003e \u003cp\u003e2.13.2 HBM Small Step Stress – Data Analysis Methods 38\u003c\/p\u003e \u003cp\u003e2.13.3 HBM Small Step Stress – Design Optimization 38\u003c\/p\u003e \u003cp\u003e2.14 Summary and Closing Comments 38\u003c\/p\u003e \u003cp\u003eProblems 39\u003c\/p\u003e \u003cp\u003eReferences 39\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Machine Model 43\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 History 43\u003c\/p\u003e \u003cp\u003e3.2 Scope 43\u003c\/p\u003e \u003cp\u003e3.3 Purpose 43\u003c\/p\u003e \u003cp\u003e3.4 Pulse Waveform 44\u003c\/p\u003e \u003cp\u003e3.4.1 Comparison of Machine Model (MM) and Human Body Model (HBM) Pulse Waveform 44\u003c\/p\u003e \u003cp\u003e3.5 Equivalent Circuit 45\u003c\/p\u003e \u003cp\u003e3.6 Test Equipment 45\u003c\/p\u003e \u003cp\u003e3.7 Test Sequence and Procedure 47\u003c\/p\u003e \u003cp\u003e3.8 Failure Mechanisms 49\u003c\/p\u003e \u003cp\u003e3.9 mm ESD Current Paths 49\u003c\/p\u003e \u003cp\u003e3.10 mm ESD Protection Circuit Solutions 52\u003c\/p\u003e \u003cp\u003e3.11 Alternate Test Methods 55\u003c\/p\u003e \u003cp\u003e3.11.1 Small Charge Model (SCM) 55\u003c\/p\u003e \u003cp\u003e3.12 Machine Model to Human Body Model Ratio 57\u003c\/p\u003e \u003cp\u003e3.13 Machine Model Status as an ESD Standard 58\u003c\/p\u003e \u003cp\u003e3.14 Summary and Closing Comments 58\u003c\/p\u003e \u003cp\u003eProblems 59\u003c\/p\u003e \u003cp\u003eReferences 59\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Charged Device Model (CDM) 61\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 History 61\u003c\/p\u003e \u003cp\u003e4.2 Scope 61\u003c\/p\u003e \u003cp\u003e4.3 Purpose 62\u003c\/p\u003e \u003cp\u003e4.4 Pulse Waveform 62\u003c\/p\u003e \u003cp\u003e4.4.1 Charged Device Model Pulse Waveform 62\u003c\/p\u003e \u003cp\u003e4.4.2 Comparison of Charged Device Model (CDM) and Human Body Model (HBM) Pulse Waveform 63\u003c\/p\u003e \u003cp\u003e4.5 Equivalent Circuit 65\u003c\/p\u003e \u003cp\u003e4.6 Test Equipment 65\u003c\/p\u003e \u003cp\u003e4.7 Test Sequence and Procedure 67\u003c\/p\u003e \u003cp\u003e4.8 Failure Mechanisms 69\u003c\/p\u003e \u003cp\u003e4.9 CDM ESD Current Paths 70\u003c\/p\u003e \u003cp\u003e4.10 CDM ESD Protection Circuit Solutions 72\u003c\/p\u003e \u003cp\u003e4.11 Alternative Test Methods 74\u003c\/p\u003e \u003cp\u003e4.11.1 Alternative Test Methods – Socketed Device Model (SDM) 74\u003c\/p\u003e \u003cp\u003e4.12 Charged Board Model (CBM) 75\u003c\/p\u003e \u003cp\u003e4.12.1 Comparison of Charged Board Model (CBM) and Charged Device Model (CDM) Pulse Waveform 75\u003c\/p\u003e \u003cp\u003e4.12.2 Charged Board Model (CBM) as an ESD Standard 77\u003c\/p\u003e \u003cp\u003e4.13 Summary and Closing Comments 77\u003c\/p\u003e \u003cp\u003eProblems 79\u003c\/p\u003e \u003cp\u003eReferences 80\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Transmission Line Pulse (TLP) Testing 84\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 History 84\u003c\/p\u003e \u003cp\u003e5.2 Scope 85\u003c\/p\u003e \u003cp\u003e5.3 Purpose 85\u003c\/p\u003e \u003cp\u003e5.4 Pulse Waveform 86\u003c\/p\u003e \u003cp\u003e5.5 Equivalent Circuit 87\u003c\/p\u003e \u003cp\u003e5.6 Test Equipment 88\u003c\/p\u003e \u003cp\u003e5.6.1 Current Source 90\u003c\/p\u003e \u003cp\u003e5.6.2 Time Domain Reflection (TDR) 90\u003c\/p\u003e \u003cp\u003e5.6.3 Time Domain Transmission (TDT) 91\u003c\/p\u003e \u003cp\u003e5.6.4 Time Domain Reflection and Transmission (TDRT) 91\u003c\/p\u003e \u003cp\u003e5.6.5 Commercial Transmission Line Pulse (TLP) Systems 92\u003c\/p\u003e \u003cp\u003e5.7 Test Sequence and Procedure 95\u003c\/p\u003e \u003cp\u003e5.7.1 TLP Pulse Analysis 96\u003c\/p\u003e \u003cp\u003e5.7.2 Measurement Window 96\u003c\/p\u003e \u003cp\u003e5.7.3 Measurement Analysis – TDR Voltage Waveform 96\u003c\/p\u003e \u003cp\u003e5.7.4 Measurement Analysis – Time Domain Reflection (TDR) Current Waveform 97\u003c\/p\u003e \u003cp\u003e5.7.5 Measurement Analysis – Time Domain Reflection (TDR) Current–Voltage Characteristic 98\u003c\/p\u003e \u003cp\u003e5.8 TLP Pulsed I–V Characteristic 98\u003c\/p\u003e \u003cp\u003e5.8.1 TLP I–V Characteristic Key Parameters 99\u003c\/p\u003e \u003cp\u003e5.8.2 TLP Power Versus Time 99\u003c\/p\u003e \u003cp\u003e5.8.3 TLP Power Versus Time – Measurement Analysis 100\u003c\/p\u003e \u003cp\u003e5.8.4 TLP Power-to-Failure Versus Pulse Width Plot 100\u003c\/p\u003e \u003cp\u003e5.9 Alternate Methods 101\u003c\/p\u003e \u003cp\u003e5.9.1 Long Duration TLP (LD-TLP) 101\u003c\/p\u003e \u003cp\u003e5.9.2 Long Duration TLP Time Domain 102\u003c\/p\u003e \u003cp\u003e5.10 TLP-to-HBM Ratio 104\u003c\/p\u003e \u003cp\u003e5.10.1 Comparison of Transmission Line Pulse (TLP) and Human Body Model (HBM) Pulse Width 104\u003c\/p\u003e \u003cp\u003e5.11 Summary and Closing Comments 104\u003c\/p\u003e \u003cp\u003eProblems 104\u003c\/p\u003e \u003cp\u003eReferences 105\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Very Fast Transmission Line Pulse (VF-TLP) Testing 108\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 History 108\u003c\/p\u003e \u003cp\u003e6.2 Scope 108\u003c\/p\u003e \u003cp\u003e6.3 Purpose 108\u003c\/p\u003e \u003cp\u003e6.4 Pulse Waveform 109\u003c\/p\u003e \u003cp\u003e6.4.1 Comparison of VF-TLP Versus TLP Waveform 110\u003c\/p\u003e \u003cp\u003e6.5 Equivalent Circuit 111\u003c\/p\u003e \u003cp\u003e6.6 Test Equipment Configuration 111\u003c\/p\u003e \u003cp\u003e6.6.1 Current Source 112\u003c\/p\u003e \u003cp\u003e6.6.2 Time Domain Reflection (TDR) 112\u003c\/p\u003e \u003cp\u003e6.6.3 Time Domain Transmission (TDT) 112\u003c\/p\u003e \u003cp\u003e6.6.4 Time Domain Reflection and Transmission (TDRT) 113\u003c\/p\u003e \u003cp\u003e6.6.5 Early VF-TLP Systems 114\u003c\/p\u003e \u003cp\u003e6.6.6 Commercial VF-TLP Test Systems 116\u003c\/p\u003e \u003cp\u003e6.7 Test Sequence and Procedure 117\u003c\/p\u003e \u003cp\u003e6.7.1 VF-TLP Pulse Analysis 118\u003c\/p\u003e \u003cp\u003e6.7.2 Measurement Window 118\u003c\/p\u003e \u003cp\u003e6.7.3 Measurement Analysis – VF-TLP Voltage Waveform 118\u003c\/p\u003e \u003cp\u003e6.7.4 Measurement Analysis – Time Domain Reflectometry (TDR) Current Waveform 118\u003c\/p\u003e \u003cp\u003e6.7.5 Measurement Analysis – Time Domain Transmission (TDR) Current–Voltage Characteristics 119\u003c\/p\u003e \u003cp\u003e6.8 VF-TLP Pulsed I–V Characteristics 121\u003c\/p\u003e \u003cp\u003e6.8.1 VF-TLP Pulsed I–V Characteristic Key Parameters 121\u003c\/p\u003e \u003cp\u003e6.8.2 VF-TLP Power Versus Time Plot 122\u003c\/p\u003e \u003cp\u003e6.8.3 VF-TLP Power Versus Time – Measurement Analysis 123\u003c\/p\u003e \u003cp\u003e6.8.4 VF-TLP Power-to-Failure Versus Pulse Width Plot 123\u003c\/p\u003e \u003cp\u003e6.8.5 VF-TLP and TLP Power-to-Failure Plot 124\u003c\/p\u003e \u003cp\u003e6.9 Alternate Test Methods 124\u003c\/p\u003e \u003cp\u003e6.9.1 Radio Frequency (RF) VF-TLP Systems 124\u003c\/p\u003e \u003cp\u003e6.9.2 Ultrafast Transmission Line Pulse (UF-TLP) 125\u003c\/p\u003e \u003cp\u003e6.10 Summary and Closing Comments 125\u003c\/p\u003e \u003cp\u003eProblems 128\u003c\/p\u003e \u003cp\u003eReferences 128\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Iec 61000-4-2 130\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 History 130\u003c\/p\u003e \u003cp\u003e7.2 Scope 130\u003c\/p\u003e \u003cp\u003e7.3 Purpose 130\u003c\/p\u003e \u003cp\u003e7.3.1 Air Discharge 131\u003c\/p\u003e \u003cp\u003e7.3.2 Direct Contact Discharge 131\u003c\/p\u003e \u003cp\u003e7.4 Pulse Waveform 131\u003c\/p\u003e \u003cp\u003e7.4.1 Pulse Waveform Equation 132\u003c\/p\u003e \u003cp\u003e7.5 Equivalent Circuit 133\u003c\/p\u003e \u003cp\u003e7.6 Test Equipment 133\u003c\/p\u003e \u003cp\u003e7.6.1 Test Configuration 134\u003c\/p\u003e \u003cp\u003e7.6.2 ESD Guns 134\u003c\/p\u003e \u003cp\u003e7.6.3 ESD Guns – Standard Versus Discharge Module 135\u003c\/p\u003e \u003cp\u003e7.6.4 Human Body Model Versus IEC 61000-4-2 135\u003c\/p\u003e \u003cp\u003e7.7 Test Sequence and Procedure 135\u003c\/p\u003e \u003cp\u003e7.8 Failure Mechanisms 137\u003c\/p\u003e \u003cp\u003e7.9 IEC 61000-4-2 ESD Current Paths 138\u003c\/p\u003e \u003cp\u003e7.10 ESD Protection Circuitry Solutions 139\u003c\/p\u003e \u003cp\u003e7.11 Alternative Test Methods 140\u003c\/p\u003e \u003cp\u003e7.11.1 Automotive ESD Standards 141\u003c\/p\u003e \u003cp\u003e7.11.2 Medical ESD Standards 142\u003c\/p\u003e \u003cp\u003e7.11.3 Avionic ESD Standard 143\u003c\/p\u003e \u003cp\u003e7.11.4 Military-Related ESD Standard 143\u003c\/p\u003e \u003cp\u003e7.12 Summary and Closing Comments 143\u003c\/p\u003e \u003cp\u003eProblems 143\u003c\/p\u003e \u003cp\u003eReferences 144\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Human Metal Model (HMM) 147\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 History 147\u003c\/p\u003e \u003cp\u003e8.2 Scope 147\u003c\/p\u003e \u003cp\u003e8.3 Purpose 148\u003c\/p\u003e \u003cp\u003e8.4 Pulse Waveform 148\u003c\/p\u003e \u003cp\u003e8.4.1 Pulse Waveform Equation 148\u003c\/p\u003e \u003cp\u003e8.5 Equivalent Circuit 149\u003c\/p\u003e \u003cp\u003e8.6 Test Equipment 149\u003c\/p\u003e \u003cp\u003e8.7 Test Configuration 150\u003c\/p\u003e \u003cp\u003e8.7.1 Horizontal Configuration 151\u003c\/p\u003e \u003cp\u003e8.7.2 Vertical Configuration 151\u003c\/p\u003e \u003cp\u003e8.7.3 HMM Fixture Board 152\u003c\/p\u003e \u003cp\u003e8.8 Test Sequence and Procedure 153\u003c\/p\u003e \u003cp\u003e8.8.1 Current Waveform Verification 154\u003c\/p\u003e \u003cp\u003e8.8.2 Current Probe Verification Methodology 154\u003c\/p\u003e \u003cp\u003e8.8.3 Current Probe Waveform Comparison 156\u003c\/p\u003e \u003cp\u003e8.9 Failure Mechanisms 157\u003c\/p\u003e \u003cp\u003e8.10 ESD Current Paths 158\u003c\/p\u003e \u003cp\u003e8.11 ESD Protection Circuit Solutions 158\u003c\/p\u003e \u003cp\u003e8.12 Summary and Closing Comments 160\u003c\/p\u003e \u003cp\u003eProblems 160\u003c\/p\u003e \u003cp\u003eReferences 161\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Iec 61000-4-5 163\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 History 163\u003c\/p\u003e \u003cp\u003e9.2 Scope 164\u003c\/p\u003e \u003cp\u003e9.3 Purpose 164\u003c\/p\u003e \u003cp\u003e9.4 Pulse Waveform 165\u003c\/p\u003e \u003cp\u003e9.5 Equivalent Circuit 166\u003c\/p\u003e \u003cp\u003e9.6 Test Equipment 166\u003c\/p\u003e \u003cp\u003e9.7 Test Sequence and Procedure 168\u003c\/p\u003e \u003cp\u003e9.8 Failure Mechanisms 168\u003c\/p\u003e \u003cp\u003e9.9 IEC 61000-4-5 ESD Current Paths 170\u003c\/p\u003e \u003cp\u003e9.10 ESD Protection Circuit Solutions 170\u003c\/p\u003e \u003cp\u003e9.11 Alternate Test Methods 171\u003c\/p\u003e \u003cp\u003e9.12 Summary and Closing Comments 171\u003c\/p\u003e \u003cp\u003eProblems 172\u003c\/p\u003e \u003cp\u003eReferences 172\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Cable Discharge Event (CDE) 174\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 History 174\u003c\/p\u003e \u003cp\u003e10.2 Scope 175\u003c\/p\u003e \u003cp\u003e10.3 Purpose 175\u003c\/p\u003e \u003cp\u003e10.4 Cable Discharge Event – Charging, Discharging, and Pulse Waveform 175\u003c\/p\u003e \u003cp\u003e10.4.1 Charging Process 176\u003c\/p\u003e \u003cp\u003e10.4.2 Discharging Process 176\u003c\/p\u003e \u003cp\u003e10.4.3 Pulse Waveform 176\u003c\/p\u003e \u003cp\u003e10.4.4 Comparison of CDE and IEC 61000-4-2 Pulse Waveform 176\u003c\/p\u003e \u003cp\u003e10.5 Equivalent Circuit 178\u003c\/p\u003e \u003cp\u003e10.6 Test Equipment 179\u003c\/p\u003e \u003cp\u003e10.6.1 Commercial Test Systems 179\u003c\/p\u003e \u003cp\u003e10.7 Test Measurement 180\u003c\/p\u003e \u003cp\u003e10.7.1 Measurement 180\u003c\/p\u003e \u003cp\u003e10.7.2 Measurement –Transmission Line Test Generators 180\u003c\/p\u003e \u003cp\u003e10.7.3 Measurement – Low-Impedance Transmission Line Waveform 181\u003c\/p\u003e \u003cp\u003e10.7.4 Schematic Capturing System Response to Reference Waveform 182\u003c\/p\u003e \u003cp\u003e10.7.5 Tapered Transmission Lines 185\u003c\/p\u003e \u003cp\u003e10.7.6 ESD Current Sensor 185\u003c\/p\u003e \u003cp\u003e10.8 Test Procedure 185\u003c\/p\u003e \u003cp\u003e10.9 Measurement of a Cable in Different Conditions 185\u003c\/p\u003e \u003cp\u003e10.9.1 Test System Configuration and Diagram 187\u003c\/p\u003e \u003cp\u003e10.9.2 Cable Configurations – Handheld Cable 189\u003c\/p\u003e \u003cp\u003e10.9.3 Cable Configuration – Taped to Ground Plane 191\u003c\/p\u003e \u003cp\u003e10.9.4 Cable Configurations – Pulse Analysis Summary 191\u003c\/p\u003e \u003cp\u003e10.10 Transient Field Measurements 195\u003c\/p\u003e \u003cp\u003e10.10.1 Transient Field Measurement of Short-Length Cable Discharge Events 195\u003c\/p\u003e \u003cp\u003e10.10.2 Antenna-Induced Voltages 195\u003c\/p\u003e \u003cp\u003e10.11 Telecommunication Cable Discharge Test System 195\u003c\/p\u003e \u003cp\u003e10.12 Cable Discharge Current Paths 200\u003c\/p\u003e \u003cp\u003e10.13 Failure Mechanisms 200\u003c\/p\u003e \u003cp\u003e10.13.1 Cable Discharge Event Failure – Connector Failure 200\u003c\/p\u003e \u003cp\u003e10.13.2 Cable Discharge Event Failure – Printed Circuit Board 201\u003c\/p\u003e \u003cp\u003e10.13.3 Cable Discharge Event Failure – Semiconductor On-Chip 201\u003c\/p\u003e \u003cp\u003e10.13.4 Cable Discharge Event (CDE)-Induced Latchup 201\u003c\/p\u003e \u003cp\u003e10.14 Cable Discharge Event (CDE) Protection 201\u003c\/p\u003e \u003cp\u003e10.14.1 RJ-45 Connectors 202\u003c\/p\u003e \u003cp\u003e10.14.2 Printed Circuit Board Design Considerations 202\u003c\/p\u003e \u003cp\u003e10.14.3 ESD Circuitry 202\u003c\/p\u003e \u003cp\u003e10.14.4 Cable Discharge Event (CDE) ESD Protection Validation 203\u003c\/p\u003e \u003cp\u003e10.15 Alternative Test Methods 203\u003c\/p\u003e \u003cp\u003e10.16 Summary and Closing Comments 204\u003c\/p\u003e \u003cp\u003eProblems 204\u003c\/p\u003e \u003cp\u003eReferences 204\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Latchup 206\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 History 206\u003c\/p\u003e \u003cp\u003e11.2 Purpose 208\u003c\/p\u003e \u003cp\u003e11.3 Scope 209\u003c\/p\u003e \u003cp\u003e11.4 Pulse Waveform 209\u003c\/p\u003e \u003cp\u003e11.5 Equivalent Circuit 209\u003c\/p\u003e \u003cp\u003e11.6 Test Equipment 209\u003c\/p\u003e \u003cp\u003e11.7 Test Sequence and Procedure 211\u003c\/p\u003e \u003cp\u003e11.8 Failure Mechanisms 215\u003c\/p\u003e \u003cp\u003e11.9 Latchup Current Paths 216\u003c\/p\u003e \u003cp\u003e11.10 Latchup Protection Solutions 216\u003c\/p\u003e \u003cp\u003e11.10.1 Latchup Protection Solutions – Semiconductor Process 219\u003c\/p\u003e \u003cp\u003e11.10.2 Latchup Protection Solutions – Design Layout 219\u003c\/p\u003e \u003cp\u003e11.10.3 Latchup Protection Solutions – Circuit Design 220\u003c\/p\u003e \u003cp\u003e11.10.4 Latchup Protection Solutions – System Level Design 221\u003c\/p\u003e \u003cp\u003e11.11 Alternate Test Methods 222\u003c\/p\u003e \u003cp\u003e11.11.1 Photoemission Techniques – PICA–TLP 222\u003c\/p\u003e \u003cp\u003e11.11.2 Photoemission Techniques – CCD Method 224\u003c\/p\u003e \u003cp\u003e11.12 Single Event Latchup (SEL) Test Methods 224\u003c\/p\u003e \u003cp\u003e11.13 Summary and Closing Comments 224\u003c\/p\u003e \u003cp\u003eProblems 227\u003c\/p\u003e \u003cp\u003eReferences 227\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Electrical Overstress (EOS) 230\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 History 230\u003c\/p\u003e \u003cp\u003e12.2 Scope 232\u003c\/p\u003e \u003cp\u003e12.3 Purpose 233\u003c\/p\u003e \u003cp\u003e12.4 Pulse Waveform 233\u003c\/p\u003e \u003cp\u003e12.5 Equivalent Circuit 233\u003c\/p\u003e \u003cp\u003e12.6 Test Equipment 234\u003c\/p\u003e \u003cp\u003e12.7 Test Procedure and Sequence 234\u003c\/p\u003e \u003cp\u003e12.8 Failure Mechanisms 236\u003c\/p\u003e \u003cp\u003e12.8.1 Information Gathering 236\u003c\/p\u003e \u003cp\u003e12.8.2 Failure Verification 237\u003c\/p\u003e \u003cp\u003e12.8.3 Failure Site Identification and Localization 237\u003c\/p\u003e \u003cp\u003e12.8.4 Root Cause Determination 238\u003c\/p\u003e \u003cp\u003e12.8.5 Feedback of Root Cause 238\u003c\/p\u003e \u003cp\u003e12.8.6 Corrective Actions 238\u003c\/p\u003e \u003cp\u003e12.8.7 Documentation Reports 238\u003c\/p\u003e \u003cp\u003e12.8.8 Statistical Analysis, Record Retention, and Control 238\u003c\/p\u003e \u003cp\u003e12.9 Electrical Overstress (EOS) Protection Circuit Solutions 240\u003c\/p\u003e \u003cp\u003e12.10 Electrical Overstress (EOS) Testing – TLP Method and EOS 249\u003c\/p\u003e \u003cp\u003e12.10.1 Electrical Overstress (EOS) Testing – Long Duration Transmission Line Pulse (LD-TLP) Method 250\u003c\/p\u003e \u003cp\u003e12.10.2 Electrical Overstress (EOS) Testing – Transmission Line Pulse (TLP) Method, EOS, and the Wunsch–Bell Model 250\u003c\/p\u003e \u003cp\u003e12.10.3 Electrical Overstress (EOS) Testing – Limitations of the Transmission Line Pulse (TLP) Method for the Evaluation of EOS for Systems 250\u003c\/p\u003e \u003cp\u003e12.10.4 Electrical Overstress (EOS) Testing – Electromagnetic Pulse (EMP) 251\u003c\/p\u003e \u003cp\u003e12.11 Electrical Overstress (EOS) Testing – DC and Transient Latchup Testing 252\u003c\/p\u003e \u003cp\u003e12.12 Summary and Closing Comments 252\u003c\/p\u003e \u003cp\u003eProblems 252\u003c\/p\u003e \u003cp\u003eReferences 253\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Electromagnetic Compatibility (EMC) 257\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 History 257\u003c\/p\u003e \u003cp\u003e13.2 Purpose 258\u003c\/p\u003e \u003cp\u003e13.3 Scope 258\u003c\/p\u003e \u003cp\u003e13.4 Pulse Waveform 258\u003c\/p\u003e \u003cp\u003e13.5 Equivalent Circuit 259\u003c\/p\u003e \u003cp\u003e13.6 Test Equipment 259\u003c\/p\u003e \u003cp\u003e13.6.1 Commercial Test System 259\u003c\/p\u003e \u003cp\u003e13.6.2 Scanning Systems 260\u003c\/p\u003e \u003cp\u003e13.7 Test Procedures 261\u003c\/p\u003e \u003cp\u003e13.7.1 ESD\/EMC Scanning Test Procedure and Method 261\u003c\/p\u003e \u003cp\u003e13.8 Failure Mechanisms 261\u003c\/p\u003e \u003cp\u003e13.9 ESD\/EMC Current Paths 263\u003c\/p\u003e \u003cp\u003e13.10 EMC Solutions 264\u003c\/p\u003e \u003cp\u003e13.11 Alternative Test Methods 266\u003c\/p\u003e \u003cp\u003e13.11.1 Scanning Methodologies 266\u003c\/p\u003e \u003cp\u003e13.11.2 Testing – Susceptibility and Vulnerability 266\u003c\/p\u003e \u003cp\u003e13.11.3 EMC\/ESD Scanning – Semiconductor Component and Populated Printed Circuit Board 267\u003c\/p\u003e \u003cp\u003e13.12 EMC\/ESD Product Evaluation – IC Prequalification 267\u003c\/p\u003e \u003cp\u003e13.13 EMC\/ESD Scanning Detection – Upset Evaluation 267\u003c\/p\u003e \u003cp\u003e13.13.1 ESD\/EMC Scanning Stimulus 267\u003c\/p\u003e \u003cp\u003e13.14 EMC\/ESD Product Qualification Process 268\u003c\/p\u003e \u003cp\u003e13.14.1 EMC\/ESD Reproducibility 268\u003c\/p\u003e \u003cp\u003e13.14.2 EMC\/ESD Failure Threshold Mapping and Histogram 268\u003c\/p\u003e \u003cp\u003e13.14.3 ESD Immunity Test – IC Level 268\u003c\/p\u003e \u003cp\u003e13.14.4 ESD Immunity Test – ATE Stage 271\u003c\/p\u003e \u003cp\u003e13.15 Alternative ESD\/EMC Scanning Methods 271\u003c\/p\u003e \u003cp\u003e13.15.1 Alternative ESD\/EMC Scanning Methods – Printed Circuit Board 271\u003c\/p\u003e \u003cp\u003e13.15.2 Electromagnetic Interference (EMI) Emission Scanning Methodology 274\u003c\/p\u003e \u003cp\u003e13.15.3 Radio Frequency (RF) Immunity Scanning Methodology 274\u003c\/p\u003e \u003cp\u003e13.15.4 Resonance Scanning Methodology 275\u003c\/p\u003e \u003cp\u003e13.15.5 Current Spreading Scanning Methodology 275\u003c\/p\u003e \u003cp\u003e13.16 Current Reconstruction Methodology 276\u003c\/p\u003e \u003cp\u003e13.16.1 EOS and Residual Current 276\u003c\/p\u003e \u003cp\u003e13.16.2 Printed Circuit Board (PCB) Trace Electromagnetic Emissions 276\u003c\/p\u003e \u003cp\u003e13.16.3 Test Procedure and Sequence 277\u003c\/p\u003e \u003cp\u003e13.17 Printed Circuit Board (PCB) Design EMC Solutions 277\u003c\/p\u003e \u003cp\u003e13.18 Summary and Closing Comments 280\u003c\/p\u003e \u003cp\u003eProblems 281\u003c\/p\u003e \u003cp\u003eReferences 282\u003c\/p\u003e \u003cp\u003eA Glossary of Terms 284\u003c\/p\u003e \u003cp\u003eB Standards 288\u003c\/p\u003e \u003cp\u003eB. 1 ESD Association 288\u003c\/p\u003e \u003cp\u003eB. 2 International Organization of Standards 289\u003c\/p\u003e \u003cp\u003eB. 3 Iec 289\u003c\/p\u003e \u003cp\u003eB. 4 Rtca 289\u003c\/p\u003e \u003cp\u003eB. 5 Department of Defense 289\u003c\/p\u003e \u003cp\u003eB. 6 Military Standards 289\u003c\/p\u003e \u003cp\u003eB. 7 Airborne Standards and Lightning 290\u003c\/p\u003e \u003cp\u003eIndex 291\u003c\/p\u003e \u003cp\u003e\u003cb\u003eDr Steven H. Voldman, IEEE Fellow, Vermont, USA\u003c\/b\u003e\u003cbr\u003eDr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for \"Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology.\" Voldman was a member of the semiconductor development of IBM for 25 years as well as a consultant for TSMC, and Samsung Electronics. Dr. Voldman initiated the first transmission line pulse (TLP) standard development team, and a participant in the JEDEC-ESD Association standards harmonization of the human body model (HBM) Standard. From 2000 to 2013, as Chairman of the ESD Association Work Group on TLP and very-fast TLP (VF-TLP), his team was responsible for initiating the first standard practice and standards for TLP and VF-TLP. He initiated the \"ESD on Campus\" program which was established to bring ESD lectures and interaction to university faculty and students internationally; the ESD on Campus program has reached over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, and China. Dr. Voldman teaches short courses and tutorials on ESD, latchup, patenting, and invention.\u003c\/p\u003e \u003cp\u003eWith the evolution of semiconductor technology and global diversification of the semiconductor business, testing of semiconductor devices to systems for electrostatic discharge (ESD) and electrical overstress (EOS) has increased in importance.\u003c\/p\u003e \u003cp\u003e\u003ci\u003eESD Testing: From Components to Systems\u003c\/i\u003e updates the reader in the new tests, test models, and techniques in the characterization of semiconductor components for ESD, EOS, and latchup.\u003c\/p\u003e \u003cp\u003e\u003cb\u003eKey features:\u003c\/b\u003e\u003c\/p\u003e \u003cul\u003e \u003cli\u003eProvides understanding and knowledge of ESD models and specifications including human body model (HBM), machine model (MM), charged device model (CDM), charged board model (CBM), cable discharge events (CDE), human metal model (HMM), IEC 61000-4-2 and IEC 61000-4-5.\u003c\/li\u003e \u003cli\u003eDiscusses new testing methodologies such as transmission line pulse (TLP), to very fast transmission line pulse (VF-TLP), and future methods of long pulse TLP, to ultra-fast TLP (UF-TLP).\u003c\/li\u003e \u003cli\u003eDescribes both conventional testing and new testing techniques for both chip and system level evaluation.\u003c\/li\u003e \u003cli\u003eAddresses EOS testing, electromagnetic compatibility (EMC) scanning, to current reconstruction methods.\u003c\/li\u003e \u003cli\u003eDiscusses latchup characterization and testing methodologies for evaluation of semiconductor technology to product testing.\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003e\u003ci\u003eESD Testing: From Components to Systems\u003c\/i\u003e is part of the authors’ series of books on electrostatic discharge (ESD) protection; this book will be an invaluable reference for the professional semiconductor chip and system-level ESD and EOS test engineer. Semiconductor device and process development, circuit designers, quality, reliability and failure analysis engineers will also find it an essential reference. In addition, its academic treatment will appeal to both senior and graduate students with interests in semiconductor process, device physics, semiconductor testing and experimental work.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47989154382053,"sku":"NP9780470511916","price":134.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780470511916.jpg?v=1761783017","url":"https:\/\/k12savings.com\/es\/products\/esd-testing-isbn-9780470511916","provider":"K12savings","version":"1.0","type":"link"}