{"product_id":"emerging-nanoelectronic-devices-isbn-9781118447741","title":"Emerging Nanoelectronic Devices","description":"\u003cp\u003e\u003ci\u003eEmerging Nanoelectronic Devices\u003c\/i\u003e focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future.  This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh perspective on emerging research devices in 26 up to date chapters written by the leading researchers in their respective areas. It supplements and extends the work performed by the Emerging Research Devices working group of the International Technology Roadmap for Semiconductors (ITRS). \u003c\/p\u003e \u003cp\u003eKey features: \u003c\/p\u003e \u003cp\u003e• Serves as an authoritative tutorial on innovative devices and architectures that populate the dynamic world of “Beyond CMOS” technologies.\u003cbr\u003e• Provides a realistic assessment of the strengths, weaknesses and key unknowns associated with each technology.\u003cbr\u003e• Suggests guidelines for the directions of future development of each technology.\u003cbr\u003e• Emphasizes physical concepts over mathematical development.\u003cbr\u003e• Provides an essential resource for students, researchers and practicing engineers.\u003c\/p\u003e  \u003cp\u003ePreface xix\u003c\/p\u003e \u003cp\u003eList of Contributors xxi\u003c\/p\u003e \u003cp\u003eAcronyms xxiii\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART ONE INTRODUCTION 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 The Nanoelectronics Roadmap 3\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eJames Hutchby\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e1.1 Introduction 3\u003c\/p\u003e \u003cp\u003e1.2 Technology Scaling: Impact and Issues 4\u003c\/p\u003e \u003cp\u003e1.3 Technology Scaling: Scaling Limits of Charge-based Devices 4\u003c\/p\u003e \u003cp\u003e1.4 The International Technology Roadmap for Semiconductors 6\u003c\/p\u003e \u003cp\u003e1.5 ITRS Emerging Research Devices International Technology Working Group 7\u003c\/p\u003e \u003cp\u003e1.6 Guiding Performance Criteria 8\u003c\/p\u003e \u003cp\u003e1.7 Selection of Nanodevices as Technology Entries 13\u003c\/p\u003e \u003cp\u003e1.8 Perspectives 13\u003c\/p\u003e \u003cp\u003eReferences 14\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 What Constitutes a Nanoswitch? A Perspective 15\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eSupriyo Datta, Vinh Quang Diep, and Behtash Behin-Aein\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e2.1 The Search for a Better Switch 15\u003c\/p\u003e \u003cp\u003e2.2 Complementary Metal Oxide Semiconductor Switch: Why it Shows Gain 17\u003c\/p\u003e \u003cp\u003e2.3 Switch Based on Magnetic Tunnel Junctions: Would it Show Gain? 20\u003c\/p\u003e \u003cp\u003e2.4 Giant Spin Hall Effect: A Route to Gain 23\u003c\/p\u003e \u003cp\u003e2.5 Other Possibilities for Switches with Gain 27\u003c\/p\u003e \u003cp\u003e2.6 What do Alternative Switches Have to Offer? 29\u003c\/p\u003e \u003cp\u003e2.7 Perspective 32\u003c\/p\u003e \u003cp\u003e2.8 Summary 32\u003c\/p\u003e \u003cp\u003eAcknowledgments 32\u003c\/p\u003e \u003cp\u003eReferences 33\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART TWO NANOELECTRONIC MEMORIES 35\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Memory Technologies: Status and Perspectives 37\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eVictor V. Zhirnov and Matthew J. Marinella\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e3.1 Introduction: Baseline Memory Technologies 37\u003c\/p\u003e \u003cp\u003e3.2 Essential Physics of Charge-based Memory 38\u003c\/p\u003e \u003cp\u003e3.3 Dynamic Random Access Memory 39\u003c\/p\u003e \u003cp\u003e3.4 Flash Memory 43\u003c\/p\u003e \u003cp\u003e3.5 Static Random Access Memory 49\u003c\/p\u003e \u003cp\u003e3.6 Summary and Perspective 52\u003c\/p\u003e \u003cp\u003eAppendix: Memory Array Interconnects 52\u003c\/p\u003e \u003cp\u003eAcknowledgments 54\u003c\/p\u003e \u003cp\u003eReferences 54\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Spin Transfer Torque Random Access Memory 56\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eJian-Ping Wang, Mahdi Jamali, Angeline Klemm, and Hao Meng\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e4.1 Chapter Overview 56\u003c\/p\u003e \u003cp\u003e4.2 Spin Transfer Torque 57\u003c\/p\u003e \u003cp\u003e4.3 STT-RAM Operation 60\u003c\/p\u003e \u003cp\u003e4.4 STT-RAM with Perpendicular Anisotropy 63\u003c\/p\u003e \u003cp\u003e4.5 Stack and Material Engineering for Jc Reduction 66\u003c\/p\u003e \u003cp\u003e4.6 Ultra-Fast Switching of MTJs 71\u003c\/p\u003e \u003cp\u003e4.7 Spin–Orbit Torques for Memory Application 72\u003c\/p\u003e \u003cp\u003e4.8 Current Demonstrations for STT-RAM 73\u003c\/p\u003e \u003cp\u003e4.9 Summary and Perspectives 73\u003c\/p\u003e \u003cp\u003eReferences 74\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Phase Change Memory 78\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eRakesh Jeyasingh, Ethan C. Ahn, S. Burc Eryilmaz, Scott Fong, and H.-S. Philip Wong\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e5.1 Introduction 78\u003c\/p\u003e \u003cp\u003e5.2 Device Operation 79\u003c\/p\u003e \u003cp\u003e5.3 Material Properties 80\u003c\/p\u003e \u003cp\u003e5.4 Device and Material Scaling to the Nanometer Size 88\u003c\/p\u003e \u003cp\u003e5.5 Multi-Bit Operation and 3D Integration 93\u003c\/p\u003e \u003cp\u003e5.6 Applications 97\u003c\/p\u003e \u003cp\u003e5.7 Future Outlook 100\u003c\/p\u003e \u003cp\u003e5.8 Summary 103\u003c\/p\u003e \u003cp\u003eAcknowledgments 103\u003c\/p\u003e \u003cp\u003eReferences 103\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Ferroelectric FET Memory 110\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eKen Takeuchi and An Chen\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e6.1 Introduction 110\u003c\/p\u003e \u003cp\u003e6.2 Ferroelectric FET for Flash Memory Application 111\u003c\/p\u003e \u003cp\u003e6.3 Ferroelectric FET for SRAM Application 115\u003c\/p\u003e \u003cp\u003e6.4 System Consideration: SSD System with Fe-NAND Flash Memory 118\u003c\/p\u003e \u003cp\u003e6.5 Perspectives and Summary 119\u003c\/p\u003e \u003cp\u003eReferences 120\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Nano-Electro-Mechanical (NEM) Memory Devices 123\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAdrian M. Ionescu\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e7.1 Introduction and Rationale for a Memory Based on NEM Switch 123\u003c\/p\u003e \u003cp\u003e7.2 NEM Relay and Capacitor Memories 126\u003c\/p\u003e \u003cp\u003e7.3 NEM-FET Memory 130\u003c\/p\u003e \u003cp\u003e7.4 Carbon-based NEM Memories 132\u003c\/p\u003e \u003cp\u003e7.5 Opportunities and Challenges for NEM Memories 133\u003c\/p\u003e \u003cp\u003eReferences 135\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Redox-based Resistive Memory 137\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eStephan Menzel, Eike Linn, and Rainer Waser\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e8.1 Introduction 137\u003c\/p\u003e \u003cp\u003e8.2 Physical Fundamentals of Redox Memories 139\u003c\/p\u003e \u003cp\u003e8.3 Electrochemical Metallization Memory Cells 144\u003c\/p\u003e \u003cp\u003e8.4 Valence Change Memory Cells 149\u003c\/p\u003e \u003cp\u003e8.5 Performance 154\u003c\/p\u003e \u003cp\u003e8.6 Summary 158\u003c\/p\u003e \u003cp\u003eReferences 158\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Electronic Effect Resistive Switching Memories 162\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAn Chen\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e9.1 Introduction 162\u003c\/p\u003e \u003cp\u003e9.2 Charge Injection and Trapping 164\u003c\/p\u003e \u003cp\u003e9.3 Mott Transition 167\u003c\/p\u003e \u003cp\u003e9.4 Ferroelectric Resistive Switching 170\u003c\/p\u003e \u003cp\u003e9.5 Perspectives 173\u003c\/p\u003e \u003cp\u003e9.6 Summary 176\u003c\/p\u003e \u003cp\u003eReferences 176\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Macromolecular Memory 181\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eBenjamin F. Bory and Stefan C.J. Meskers\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e10.1 Chapter Overview 181\u003c\/p\u003e \u003cp\u003e10.2 Macromolecules 181\u003c\/p\u003e \u003cp\u003e10.3 Elementary Physical Chemistry of Macromolecular Memory 184\u003c\/p\u003e \u003cp\u003e10.4 Classes of Macromolecular Memory Materials and Their Performance 187\u003c\/p\u003e \u003cp\u003e10.5 Perspectives 190\u003c\/p\u003e \u003cp\u003e10.6 Summary 190\u003c\/p\u003e \u003cp\u003eAcknowledgments 190\u003c\/p\u003e \u003cp\u003eReferences 191\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Molecular Transistors 194\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eMark A. Reed, Hyunwook Song, and Takhee Lee\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e11.1 Introduction 194\u003c\/p\u003e \u003cp\u003e11.2 Experimental Approaches 194\u003c\/p\u003e \u003cp\u003e11.3 Molecular Transistors 213\u003c\/p\u003e \u003cp\u003e11.4 Molecular Design 218\u003c\/p\u003e \u003cp\u003e11.5 Perspectives 222\u003c\/p\u003e \u003cp\u003eAcknowledgments 223\u003c\/p\u003e \u003cp\u003eReferences 223\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Memory Select Devices 227\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAn Chen\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e12.1 Introduction 227\u003c\/p\u003e \u003cp\u003e12.2 Crossbar Array and Memory Select Devices 227\u003c\/p\u003e \u003cp\u003e12.3 Memory Select Device Options 230\u003c\/p\u003e \u003cp\u003e12.4 Challenges of Memory Select Devices 241\u003c\/p\u003e \u003cp\u003e12.5 Summary 242\u003c\/p\u003e \u003cp\u003eReferences 242\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Emerging Memory Devices: Assessment and Benchmarking 246\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eMatthew J. Marinella and Victor V. Zhirnov\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e13.1 Introduction 246\u003c\/p\u003e \u003cp\u003e13.2 Common Emerging Memory Terminology and Metrics 248\u003c\/p\u003e \u003cp\u003e13.3 Redox RAM 249\u003c\/p\u003e \u003cp\u003e13.4 Emerging Ferroelectric Memories 254\u003c\/p\u003e \u003cp\u003e13.5 Mott Memory 258\u003c\/p\u003e \u003cp\u003e13.6 Macromolecular Memory 259\u003c\/p\u003e \u003cp\u003e13.7 Carbon-based Resistive Switching Memory 260\u003c\/p\u003e \u003cp\u003e13.8 Molecular Memory 262\u003c\/p\u003e \u003cp\u003e13.9 Assessment and Benchmarking 263\u003c\/p\u003e \u003cp\u003e13.10 Summary and Conclusions 271\u003c\/p\u003e \u003cp\u003eAcknowledgments 271\u003c\/p\u003e \u003cp\u003eReferences 271\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART THREE NANOELECTRONIC LOGIC AND INFORMATION PROCESSING 277\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e14 Re-Invention of FET 279\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eToshiro Hiramoto\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e14.1 Introduction 279\u003c\/p\u003e \u003cp\u003e14.2 Historical and Future Trend of MOSFETs 279\u003c\/p\u003e \u003cp\u003e14.3 Near-term Solutions 282\u003c\/p\u003e \u003cp\u003e14.4 Long-term Solutions 285\u003c\/p\u003e \u003cp\u003e14.5 Summary 295\u003c\/p\u003e \u003cp\u003eReferences 296\u003c\/p\u003e \u003cp\u003e\u003cb\u003e15 Graphene Electronics 298\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eFrank Schwierz\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e15.1 Introduction 298\u003c\/p\u003e \u003cp\u003e15.2 Properties of Graphene 300\u003c\/p\u003e \u003cp\u003e15.3 Graphene MOSFETs for Mainstream Logic and RF Applications 303\u003c\/p\u003e \u003cp\u003e15.4 Graphene MOSFETs for Nonmainstream Applications 308\u003c\/p\u003e \u003cp\u003e15.5 Graphene NonMOSFET Transistors 309\u003c\/p\u003e \u003cp\u003e15.6 Perspectives 310\u003c\/p\u003e \u003cp\u003eAcknowledgment 311\u003c\/p\u003e \u003cp\u003eReferences 311\u003c\/p\u003e \u003cp\u003e\u003cb\u003e16 Carbon Nanotube Electronics 315\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAaron D. Franklin\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e16.1 Carbon Nanotubes – The Ideal Transistor Channel 315\u003c\/p\u003e \u003cp\u003e16.2 Operation of the CNTFET 319\u003c\/p\u003e \u003cp\u003e16.3 Important Aspects of CNTFETs 320\u003c\/p\u003e \u003cp\u003e16.4 Scaling CNTFETs to the Sub-10 Nanometer Regime 324\u003c\/p\u003e \u003cp\u003e16.5 Material Considerations 327\u003c\/p\u003e \u003cp\u003e16.6 Perspective 329\u003c\/p\u003e \u003cp\u003e16.7 Conclusion 331\u003c\/p\u003e \u003cp\u003eReferences 331\u003c\/p\u003e \u003cp\u003e\u003cb\u003e17 Spintronics 336\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAlexander Khitun\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e17.1 Introduction 336\u003c\/p\u003e \u003cp\u003e17.2 Spin Transistors 337\u003c\/p\u003e \u003cp\u003e17.3 Magnetic Logic Circuits 348\u003c\/p\u003e \u003cp\u003e17.4 Summary 364\u003c\/p\u003e \u003cp\u003eReferences 365\u003c\/p\u003e \u003cp\u003e\u003cb\u003e18 NEMS Switch Technology 370\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eLouis Hutin and Tsu-Jae King Liu\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e18.1 Electromechanical Switches for Digital Logic 370\u003c\/p\u003e \u003cp\u003e18.2 Actuation Mechanisms 373\u003c\/p\u003e \u003cp\u003e18.3 Electrostatic Switch Designs 379\u003c\/p\u003e \u003cp\u003e18.4 Reliability and Scalability 383\u003c\/p\u003e \u003cp\u003eReferences 386\u003c\/p\u003e \u003cp\u003e\u003cb\u003e19 Atomic Switch 390\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eTsuyoshi Hasegawa and Masakazu Aono\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e19.1 Chapter Overview 390\u003c\/p\u003e \u003cp\u003e19.2 Historical Background of the Atomic Switch 390\u003c\/p\u003e \u003cp\u003e19.3 Fundamentals of Atomic Switches 391\u003c\/p\u003e \u003cp\u003e19.4 Various Atomic Switches 395\u003c\/p\u003e \u003cp\u003e19.5 Perspectives 401\u003c\/p\u003e \u003cp\u003eReferences 402\u003c\/p\u003e \u003cp\u003e\u003cb\u003e20 ITRS Assessment and Benchmarking of Emerging Logic Devices 405\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eShamik Das\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e20.1 Introduction 405\u003c\/p\u003e \u003cp\u003e20.2 Overview of the ITRS Roadmap for Emerging Research Logic Devices 406\u003c\/p\u003e \u003cp\u003e20.3 Recent Results for Selected Emerging Devices 407\u003c\/p\u003e \u003cp\u003e20.4 Perspective 412\u003c\/p\u003e \u003cp\u003e20.5 Summary 413\u003c\/p\u003e \u003cp\u003eAcknowledgments 413\u003c\/p\u003e \u003cp\u003eReferences 413\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART FOUR CONCEPTS FOR EMERGING ARCHITECTURES 417\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e21 Nanomagnet Logic: A Magnetic Implementation of Quantum-dot Cellular Automata 419\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eMichael T. Niemier, György Csaba, and Wolfgang Porod\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e21.1 Introduction 419\u003c\/p\u003e \u003cp\u003e21.2 Technology Background 420\u003c\/p\u003e \u003cp\u003e21.3 NML Circuit Design Based on Conventional, Boolean Logic Gates 423\u003c\/p\u003e \u003cp\u003e21.4 Alternative Circuit Design Techniques and Architectures 432\u003c\/p\u003e \u003cp\u003e21.5 Retrospective, Future Challenges, and Future Research Directions 437\u003c\/p\u003e \u003cp\u003eReferences 439\u003c\/p\u003e \u003cp\u003e\u003cb\u003e22 Explorations in Morphic Architectures 443\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eTetsuya Asai and Ferdinand Peper\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e22.1 Introduction 443\u003c\/p\u003e \u003cp\u003e22.2 Neuromorphic Architectures 443\u003c\/p\u003e \u003cp\u003e22.3 Cellular Automata Architectures 447\u003c\/p\u003e \u003cp\u003e22.4 Taxonomy of Computational Ability of Architectures 450\u003c\/p\u003e \u003cp\u003e22.5 Summary 452\u003c\/p\u003e \u003cp\u003eReferences 452\u003c\/p\u003e \u003cp\u003e\u003cb\u003e23 Design Considerations for a Computational Architecture of Human Cognition 456\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eNarayan Srinivasa\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e23.1 Introduction 456\u003c\/p\u003e \u003cp\u003e23.2 Features of Biological Computation 457\u003c\/p\u003e \u003cp\u003e23.3 Evolution of Behavior as a Basis for Cognitive Architecture Design 460\u003c\/p\u003e \u003cp\u003e23.4 Considerations for a Cognitive Architecture 460\u003c\/p\u003e \u003cp\u003e23.5 Emergent Cognition 463\u003c\/p\u003e \u003cp\u003e23.6 Perspectives 463\u003c\/p\u003e \u003cp\u003eReferences 464\u003c\/p\u003e \u003cp\u003e\u003cb\u003e24 Alternative Architectures for NonBoolean Information Processing Systems 467\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eYan Fang, Steven P. Levitan, Donald M. Chiarulli, and Denver H. Dash\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e24.1 Introduction 467\u003c\/p\u003e \u003cp\u003e24.2 Hierarchical Associative Memory Models 475\u003c\/p\u003e \u003cp\u003e24.3 N-Tree Model 484\u003c\/p\u003e \u003cp\u003e24.4 Summary and Conclusion 494\u003c\/p\u003e \u003cp\u003eAcknowledgments 496\u003c\/p\u003e \u003cp\u003eReferences 496\u003c\/p\u003e \u003cp\u003e\u003cb\u003e25 Storage Class Memory 498\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eGeoffrey W. Burr and Paul Franzon\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e25.1 Introduction 498\u003c\/p\u003e \u003cp\u003e25.2 Traditional Storage: HDD and Flash Solid-state Drives 499\u003c\/p\u003e \u003cp\u003e25.3 What is Storage Class Memory? 499\u003c\/p\u003e \u003cp\u003e25.4 Target Specifications for SCM 501\u003c\/p\u003e \u003cp\u003e25.5 Device Candidates for SCM 502\u003c\/p\u003e \u003cp\u003e25.6 Architectural Issues in SCM 504\u003c\/p\u003e \u003cp\u003e25.7 Conclusions 508\u003c\/p\u003e \u003cp\u003eReferences 509\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePART FIVE SUMMARY, CONCLUSIONS, AND OUTLOOK FOR NANOELECTRONIC DEVICES 511\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003e26 Outlook for Nanoelectronic Devices 513\u003c\/b\u003e\u003cbr\u003e \u003ci\u003eAn Chen, James Hutchby, Victor V. Zhirnov, and George Bourianoff\u003c\/i\u003e\u003c\/p\u003e \u003cp\u003e26.1 Introduction 513\u003c\/p\u003e \u003cp\u003e26.2 Quantitative Logic Benchmarking for Beyond CMOS Technologies 514\u003c\/p\u003e \u003cp\u003e26.3 Survey-based Critical Assessment of Emerging Devices 518\u003c\/p\u003e \u003cp\u003e26.4 Retrospective Assessment of ERD Tracked Technologies 526\u003c\/p\u003e \u003cp\u003eReferences 528\u003c\/p\u003e \u003cp\u003eIndex 529\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eAn Chen\u003c\/b\u003e is with GLOBALFOUNDRIES, working on emerging logic and memory technologies.  He is the Memory Technology Lead responsible for exploratory memory research with industrial consortia including IMEC and Sematech.  His memory research focuses primarily on RRAM and STTRAM.  Prior to GLOBALFOUNDRIES, he worked at Spansion LLC on emerging memory research and at Advanced Micro Devices (AMD) on nanoelectronics.  He is currently chairing the Emerging Research Device (ERD) working group in the International Technology Roadmap of Semiconductors (ITRS).  He is also a Senior Member of the IEEE. \u003c\/p\u003e \u003cp\u003e\u003cb\u003eJames Hutchby,\u003c\/b\u003e Senior Scientist, Emeritus, was formerly Director of Device Sciences of Semiconductor Research Corporation (SRC). Prior to joining SRC he was founding Director of the Research Triangle Institute’s Center for Semiconductor Research, which consisted of five research groups performing research on: low-temperature growth of diamond; high efficiency multi-bandgap solar cells; complementary HBT devices and integrated circuits and high efficiency thermoelectrics and theremovoltaics. Dr Hutchby has authored or co-authored over 160 contributed and invited papers.  He is also a Life Fellow of the IEEE and a recipient of the IEEE Third Millennium Medal. \u003c\/p\u003e \u003cp\u003e\u003cb\u003eVictor Zhirnov\u003c\/b\u003e is Director of Special Projects at the SRC. His research interests include nanoelectronics devices and systems, properties of materials at the nanoscale and bio-inspired electronic systems. He also holds an adjunct faculty position at North Carolina State University and has served as an advisor to a number of government, industrial, and academic institutions. Victor Zhirnov has authored and co-authored over 100 technical papers and contributions to books. \u003c\/p\u003e \u003cp\u003e\u003cb\u003eGeorge Bourianoff\u003c\/b\u003e is a Senior Principle Engineer in the Components Research group at Intel. He is responsible for developing and managing research programs in emerging research technologies and architectures.  He also serves on the scientific advisory boards of the Nanoelectronic Research Initiative (NRI) and the Semiconductor Technology Advanced Research Network. (STARnet).  Prior to joining Intel in 1994 Dr Bourianoff was a group leader in the Superconducting Supercollidier Project in Texas responsible for accelerator simulation.  Prior to that, he was a Senior Scientist with SAIC responsible for Magneto Hydrodynamic code development.\u003c\/p\u003e  \u003cp\u003e\u003ci\u003eEmerging Nanoelectronic Devices\u003c\/i\u003e focuses on the future direction of semiconductor and emerging nanoscale device technology. As the dimensional scaling of CMOS approaches its limits, alternate information processing devices and microarchitectures are being explored to sustain increasing functionality at decreasing cost into the indefinite future.  This is driving new paradigms of information processing enabled by innovative new devices, circuits, and architectures, necessary to support an increasingly interconnected world through a rapidly evolving internet. This original title provides a fresh perspective on emerging research devices in 26 up to date chapters written by the leading researchers in their respective areas. It supplements and extends the work performed by the Emerging Research Devices working group of the International Technology Roadmap for Semiconductors (ITRS).\u003cbr\u003e \u003cbr\u003e \u003cb\u003eKey features:\u003c\/b\u003e\u003c\/p\u003e \u003cul\u003e \u003cli\u003eServes as an authoritative tutorial on innovative devices and architectures that populate the dynamic world of “Beyond CMOS” technologies.\u003c\/li\u003e \u003cli\u003eProvides a realistic assessment of the strengths, weaknesses and key unknowns associated with each technology.\u003c\/li\u003e \u003cli\u003eSuggests guidelines for the directions of future development of each technology.\u003c\/li\u003e \u003cli\u003eEmphasizes physical concepts over mathematical development.\u003c\/li\u003e \u003cli\u003eProvides an essential resource for students, researchers and practicing engineers.\u003c\/li\u003e \u003c\/ul\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47989122957541,"sku":"NP9781118447741","price":145.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781118447741.jpg?v=1761782887","url":"https:\/\/k12savings.com\/es\/products\/emerging-nanoelectronic-devices-isbn-9781118447741","provider":"K12savings","version":"1.0","type":"link"}