{"product_id":"embedded-sopc-design-with-nios-ii-processor-and-verilog-examples-isbn-9781118011034","title":"Embedded SoPC Design with Nios II Processor and Verilog Examples","description":"\u003cp\u003e\u003cb\u003eExplores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog\u003c\/b\u003e \u003c\/p\u003e\u003cp\u003eAn SoPC (system on a programmable chip) integrates a processor, memory modules, I\/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well—allowing us to configure the soft-core processor, create tailored I\/O interfaces, and develop specialized hardware accelerators for computation-intensive tasks. \u003c\/p\u003e\u003cp\u003eUtilizing an Altera FPGA prototyping board and its Nios II soft-core processor, \u003ci\u003eEmbedded SoPC Design with Nios II Processor and Verilog Examples\u003c\/i\u003e takes a \"learn by doing\" approach to illustrate the hardware and software design and development process by including realistic projects that can be implemented and tested on the board. \u003c\/p\u003e\u003cp\u003eEmphasizing hardware design and integration throughout, the book is divided into four major parts: \u003c\/p\u003e\u003cul\u003e \u003cli\u003ePart I covers HDL and synthesis of custom hardware\u003c\/li\u003e \u003cli\u003ePart II introduces the Nios II processor and provides an overview of embedded software development\u003c\/li\u003e \u003cli\u003ePart III demonstrates the design and development of hardware and software of several complex I\/O peripherals, including a PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card\u003c\/li\u003e \u003cli\u003ePart IV provides several case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eWhile designing and developing an embedded SoPC can be rewarding, the learning can be a long and winding journey. This book shows the trail ahead and guides readers through the initial steps to exploit the full potential of this emerging methodology. \u003c\/p\u003e\u003cp\u003ePreface xxvii\u003c\/p\u003e \u003cp\u003eAcknowledgments\u003c\/p\u003e \u003cp\u003e1 Overview of Embedded System 1\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart I: Basic Digital Circuits Development\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2 Gate-level Combinational Circuit 11\u003c\/p\u003e \u003cp\u003e3 Overview of FPGA and EDA Software 25\u003c\/p\u003e \u003cp\u003e4 RT-level Combinational Circuit 53\u003c\/p\u003e \u003cp\u003e5 Regular Sequential Circuit 93\u003c\/p\u003e \u003cp\u003e6 FSM 137\u003c\/p\u003e \u003cp\u003e7 FSMD 155\u003c\/p\u003e \u003cp\u003e8 Selected Topics of Verilog 188\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart II: Basic Nois II Software Development\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9 Nios II Processor Overview 229\u003c\/p\u003e \u003cp\u003e10 NIOS II System Derivation and Low-Level Access 237\u003c\/p\u003e \u003cp\u003e11 Predesigned Nios II I\/O Peripherals 265  \u003c\/p\u003e \u003cp\u003e12 Predesigned Nios II I\/O Drivers and HAL API 303\u003c\/p\u003e \u003cp\u003e13 Interrupt and ISR 325\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart III: Custom I\/O Peripheral Development \u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e14 Custom I\/O Peripheral with PIO Cores 345\u003c\/p\u003e \u003cp\u003e15 Avalon Interconnect and SOPC Component 351\u003c\/p\u003e \u003cp\u003e16 SRAM and SDRAM Controllers 385\u003c\/p\u003e \u003cp\u003e17 PS2 Keyboard and Mouse 423\u003c\/p\u003e \u003cp\u003e18 VGA Controller 475\u003c\/p\u003e \u003cp\u003e19 Audio Codec Controller 555\u003c\/p\u003e \u003cp\u003e20 SD Card Controller 601\u003c\/p\u003e \u003cp\u003e\u003cb\u003ePart IV: Hardware Acclerator Case Studies\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e21 GCD Accelerator 663\u003c\/p\u003e \u003cp\u003e22 Mandelbrot Set Fractal Accelerator 681\u003c\/p\u003e \u003cp\u003e23 Direct Digital Frequency Synthesis 715\u003c\/p\u003e \u003cp\u003eReferences 741\u003c\/p\u003e \u003cp\u003eTopic Index 745\u003c\/p\u003e  \u003cp\u003e\u003cb\u003eD\u003csmall\u003eR\u003c\/small\u003e. PONG P. CHU\u003c\/b\u003e is Associate Professor in the Department of Electrical and Computer Engineering at Cleveland State University in Ohio. He has taught undergraduate- and graduate-level digital systems and computer architecture courses for more than a decade and has received instructional grants from the National Science Foundation and Cleveland State University.   \u003c\/p\u003e\u003cp\u003e\u003cb\u003eExplores the unique hardware programmability of FPGA-based embedded systems, using a learn-by-doing approach to introduce the concepts and techniques for embedded SoPC design with Verilog\u003c\/b\u003e \u003c\/p\u003e\u003cp\u003eAn SoPC (system on a programmable chip) integrates a processor, memory modules, I\/O peripherals, and custom hardware accelerators into a single FPGA (field-programmable gate array) device. In addition to the customized software, customized hardware can be developed and incorporated into the embedded system as well—allowing us to configure the soft-core processor, create tailored I\/O interfaces, and develop specialized hardware accelerators for computation-intensive tasks. \u003c\/p\u003e\u003cp\u003eUtilizing an Altera FPGA prototyping board and its Nios II soft-core processor, \u003ci\u003eEmbedded SoPC Design with Nios II Processor and Verilog Examples\u003c\/i\u003e takes a \"learn by doing\" approach to illustrate the hardware and software design and development process by including realistic projects that can be implemented and tested on the board. \u003c\/p\u003e\u003cp\u003eEmphasizing hardware design and integration throughout, the book is divided into four major parts: \u003c\/p\u003e\u003cul\u003e \u003cli\u003ePart I covers HDL and synthesis of custom hardware\u003c\/li\u003e \u003cli\u003ePart II introduces the Nios II processor and provides an overview of embedded software development\u003c\/li\u003e \u003cli\u003ePart III demonstrates the design and development of hardware and software of several complex I\/O peripherals, including a PS2 keyboard and mouse, a graphic video controller, an audio codec, and an SD (secure digital) card\u003c\/li\u003e \u003cli\u003ePart IV provides several case studies of the integration of hardware accelerators, including a custom GCD (greatest common divisor) circuit, a Mandelbrot set fractal circuit, and an audio synthesizer based on DDFS (direct digital frequency synthesis) methodology\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eWhile designing and developing an embedded SoPC can be rewarding, the learning can be a long and winding journey. This book shows the trail ahead and guides readers through the initial steps to exploit the full potential of this emerging methodology.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47989120729317,"sku":"NP9781118011034","price":155.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781118011034.jpg?v=1761782880","url":"https:\/\/k12savings.com\/es\/products\/embedded-sopc-design-with-nios-ii-processor-and-verilog-examples-isbn-9781118011034","provider":"K12savings","version":"1.0","type":"link"}