{"product_id":"digital-logic-isbn-9781119621638","title":"Digital Logic","description":"\u003cp\u003e\u003ci\u003eDigital Logic with an Introduction to Verilog and FPGA-Based Design\u003c\/i\u003e provides basic knowledge of field programmable gate array (FPGA) design and implementation using Verilog, a hardware description language (HDL) commonly used in the design and verification of digital circuits. Emphasizing fundamental principles, this student-friendly textbook is an ideal resource for introductory digital logic courses. Chapters offer clear explanations of key concepts and step-by-step procedures that illustrate the real-world application of FPGA-based design.\u003c\/p\u003e \u003cp\u003eDesigned for beginning students familiar with DC circuits and the C programming language, the text begins by describing of basic terminologies and essential concepts of digital integrated circuits using transistors. Subsequent chapters cover device level and logic level design in detail, including combinational and sequential circuits used in the design of microcontrollers and microprocessors. Topics include Boolean algebra and functions, analysis and design of sequential circuits using logic gates, FPGA-based implementation using CAD software tools, and combinational logic design using various HDLs with focus on Verilog.\u003c\/p\u003e \u003cp\u003ePreface ix\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 Introduction to Digital Systems 1\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 Explanation of Terms 2\u003c\/p\u003e \u003cp\u003e1.2 Design Levels 4\u003c\/p\u003e \u003cp\u003e1.3 Combinational vs. Sequential Systems 4\u003c\/p\u003e \u003cp\u003e1.4 Digital Circuits 5\u003c\/p\u003e \u003cp\u003e1.4.1 Diodes 5\u003c\/p\u003e \u003cp\u003e1.4.2 Transistors 5\u003c\/p\u003e \u003cp\u003e1.4.3 MOS Transistors 11\u003c\/p\u003e \u003cp\u003e1.5 Integrated Circuits (ICs) 14\u003c\/p\u003e \u003cp\u003e1.6 CAD (Computer-Aided Design) 16\u003c\/p\u003e \u003cp\u003e1.7 Evolution of Digital Logic, Microprocessors, and Microcontrollers 16\u003c\/p\u003e \u003cp\u003e1.8 A Typical Application of a Digital System such as a Microcontroller 18\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 Number Systems, Arithmetic\/Logic Operations, and Codes 21\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 Number Systems 21\u003c\/p\u003e \u003cp\u003e2.1.1 General Number Representation 21\u003c\/p\u003e \u003cp\u003e2.1.2 Converting Numbers from One Base to Another 23\u003c\/p\u003e \u003cp\u003e2.2 Unsigned and Signed Binary Numbers 27\u003c\/p\u003e \u003cp\u003e2.3 Codes 30\u003c\/p\u003e \u003cp\u003e2.3.1 Binary-Coded-Decimal Code (8421 Code) 30\u003c\/p\u003e \u003cp\u003e2.3.2 Alphanumeric Codes 31\u003c\/p\u003e \u003cp\u003e2.3.3 Excess-3 Code 31\u003c\/p\u003e \u003cp\u003e2.3.4 Gray Code 33\u003c\/p\u003e \u003cp\u003e2.3.5 Unicode 35\u003c\/p\u003e \u003cp\u003e2.4 Fixed-Point and Floating-Point Representations 35\u003c\/p\u003e \u003cp\u003e2.5 Arithmetic Operations 36\u003c\/p\u003e \u003cp\u003e2.5.1 Binary Arithmetic 36\u003c\/p\u003e \u003cp\u003e2.5.2 BCD Arithmetic 44\u003c\/p\u003e \u003cp\u003e2.5.3 Multiword Binary Addition and Subtraction 45\u003c\/p\u003e \u003cp\u003e2.5.4 Binary Multiplication and Division by Shift Operations 46\u003c\/p\u003e \u003cp\u003e2.6 Error Correction and Detection 48\u003c\/p\u003e \u003cp\u003eQuestions and Problems 50\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 Digital Logic Gates, Boolean Algebra, and Simplification 53\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 Basic Logic Operations 53\u003c\/p\u003e \u003cp\u003e3.1.1 NOT Operation 53\u003c\/p\u003e \u003cp\u003e3.1.2 OR operation 54\u003c\/p\u003e \u003cp\u003e3.1.3 AND operation 56\u003c\/p\u003e \u003cp\u003e3.2 Other Logic Operations 57\u003c\/p\u003e \u003cp\u003e3.2.1 NOR operation 57\u003c\/p\u003e \u003cp\u003e3.2.2 NAND operation 58\u003c\/p\u003e \u003cp\u003e3.2.3 Exclusive-OR operation (XOR) 59\u003c\/p\u003e \u003cp\u003e3.2.4 Exclusive-NOR Operation (XNOR) 61\u003c\/p\u003e \u003cp\u003e3.3 Positive and Negative Logic 62\u003c\/p\u003e \u003cp\u003e3.4 Boolean Algebra 63\u003c\/p\u003e \u003cp\u003e3.4.1 Boolean Identities 64\u003c\/p\u003e \u003cp\u003e3.4.2 Simplification Using Boolean Identities 65\u003c\/p\u003e \u003cp\u003e3.4.3 Consensus Theorem 69\u003c\/p\u003e \u003cp\u003e3.4.4 Getting Rid of Glitches or Hazards in Combinational Circuits 70\u003c\/p\u003e \u003cp\u003e3.4.5 Complement of a Boolean Function 71\u003c\/p\u003e \u003cp\u003e3.5 XOR \/ XNOR Implementations 71\u003c\/p\u003e \u003cp\u003eQuestions and Problems 74\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 Minterms, Maxterms, and Karnaugh Map 77\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 Standard Representations 77\u003c\/p\u003e \u003cp\u003e4.2 Karnaugh Maps 81\u003c\/p\u003e \u003cp\u003e4.2.1 Two-Variable K-map 81\u003c\/p\u003e \u003cp\u003e4.2.2 Three-Variable K-map 82\u003c\/p\u003e \u003cp\u003e4.2.3 Four-Variable K-map 84\u003c\/p\u003e \u003cp\u003e4.2.4 Prime Implicants 87\u003c\/p\u003e \u003cp\u003e4.2.5 Expressing a Boolean function in Product-of-sums (POS) form using a K-map 89\u003c\/p\u003e \u003cp\u003e4.2.6 Don’t Care Conditions 90\u003c\/p\u003e \u003cp\u003e4.2.7 Five-Variable K-map 94\u003c\/p\u003e \u003cp\u003e4.3 Quine–McCluskey Method 95\u003c\/p\u003e \u003cp\u003e4.4 Implementation of Digital Circuits with NAND, and NOR Gates 96\u003c\/p\u003e \u003cp\u003e4.4.1 NAND Gate Implementation 97\u003c\/p\u003e \u003cp\u003e4.4.2 NOR Gate Implementation 98\u003c\/p\u003e \u003cp\u003eQuestions and Problems 103\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 Analysis and Design of Combinational Circuits Using Gates 107\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 Basic Concepts 107\u003c\/p\u003e \u003cp\u003e5.2 Analysis of a Combinational Logic Circuit 107\u003c\/p\u003e \u003cp\u003e5.3 Design of Combinational Circuits Using Logic Gates 108\u003c\/p\u003e \u003cp\u003e5.4 Multiple-Output Combinational Circuits 113\u003c\/p\u003e \u003cp\u003eQuestions and Problems 118\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 Design of Typical Combinational Logic Components 121\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 Design of Typical Combinational Logic Components 121\u003c\/p\u003e \u003cp\u003e6.2 Comparators 121\u003c\/p\u003e \u003cp\u003e6.3 Decoders 124\u003c\/p\u003e \u003cp\u003e6.4 Encoders 130\u003c\/p\u003e \u003cp\u003e6.5 Multiplexers 133\u003c\/p\u003e \u003cp\u003e6.6 Demultiplexers 137\u003c\/p\u003e \u003cp\u003e6.7 Binary Adder\/Subtractor and BCD Adder 139\u003c\/p\u003e \u003cp\u003eQuestions and Problems 148\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 Combinational Shifter, Fast Adders, Array Multipliers, ALU, \u0026amp; PLDS 151\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 Combinational Shifter 151\u003c\/p\u003e \u003cp\u003e7.2 Central Processing Unit (CPU) 152\u003c\/p\u003e \u003cp\u003e7.3 Arithmetic Logic Unit (ALU) 154\u003c\/p\u003e \u003cp\u003e7.4 Read-Only Memories (ROMs) 165\u003c\/p\u003e \u003cp\u003e7.5 Programmable Logic Devices (PLDs) 167\u003c\/p\u003e \u003cp\u003e7.6 Commercially Available Field Programmable Devices (FPDs) 170\u003c\/p\u003e \u003cp\u003eQuestions and Problems 172\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 Combinational Logic Using Verilog 175\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 Hardware Description Languages (HDLs) 175\u003c\/p\u003e \u003cp\u003e8.2 Basics of Verilog 176\u003c\/p\u003e \u003cp\u003e8.2.1 Verilog keywords 176\u003c\/p\u003e \u003cp\u003e8.2.2 Representing numbers in Verilog 176\u003c\/p\u003e \u003cp\u003e8.2.3 A typical Verilog Segment 177\u003c\/p\u003e \u003cp\u003e8.3 Structural Modeling 182\u003c\/p\u003e \u003cp\u003e8.4 Dataflow Modeling 189\u003c\/p\u003e \u003cp\u003e8.5 Behavioral modeling 195\u003c\/p\u003e \u003cp\u003e8.5.1 if-else block 197\u003c\/p\u003e \u003cp\u003e8.5.2 Modeling logical conditions in a circuit 198\u003c\/p\u003e \u003cp\u003e8.5.3 Case-endcase construct 198\u003c\/p\u003e \u003cp\u003e8.5.4 Conditional Operator 200\u003c\/p\u003e \u003cp\u003e8.6 Simulation 201\u003c\/p\u003e \u003cp\u003eQuestions and Problems 207\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 Latches and Flip-Flops 211 \u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 Latches and Flip-Flops 211\u003c\/p\u003e \u003cp\u003e9.1.1 SR Latch 211\u003c\/p\u003e \u003cp\u003e9.1.2 Gated SR Latch 213\u003c\/p\u003e \u003cp\u003e9.1.3 Gated D Latch 213\u003c\/p\u003e \u003cp\u003e9.1.4 Edge-Trigerred D Flip-Flop 214\u003c\/p\u003e \u003cp\u003e9.1.5 JK Flip-Flop 216\u003c\/p\u003e \u003cp\u003e9.1.6 T Flip-Flop 217\u003c\/p\u003e \u003cp\u003e9.2 Timing parameters for edge-triggered flip-flops 218\u003c\/p\u003e \u003cp\u003e9.3 Preset and Clear Inputs 219\u003c\/p\u003e \u003cp\u003e9.4 Summary of Flip-Flops 220\u003c\/p\u003e \u003cp\u003eQuestions and Problems 224\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 Analysis and Design of Sequential Circuits 227\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 Introduction 227\u003c\/p\u003e \u003cp\u003e10.2 Analysis of Synchronous Sequential Circuits 228\u003c\/p\u003e \u003cp\u003e10.3 Types of Synchronous Sequential Circuits 233\u003c\/p\u003e \u003cp\u003e10.4 Minimization of States 235\u003c\/p\u003e \u003cp\u003e10.5 Design of Synchronous Sequential Circuits 237\u003c\/p\u003e \u003cp\u003e10.6 Serial Adder 240\u003c\/p\u003e \u003cp\u003e10.7 Sequence Generator\/Detector 242\u003c\/p\u003e \u003cp\u003e10.8 Random-Access Memory (RAM) 245\u003c\/p\u003e \u003cp\u003e10.9 Algorithmic State Machines (ASM) Chart 247\u003c\/p\u003e \u003cp\u003e10.10 Asynchronous Sequential Circuits 255\u003c\/p\u003e \u003cp\u003eQuestions and Problems 258\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 Counters and Registers 263\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 Design of Counters 263\u003c\/p\u003e \u003cp\u003e11.2 Design of Registers 268\u003c\/p\u003e \u003cp\u003e11.2.1 Shift Register 268\u003c\/p\u003e \u003cp\u003e11.2.2 “Shift register” Counters 271\u003c\/p\u003e \u003cp\u003e11.2.3 General-Purpose Register (GPR) 275\u003c\/p\u003e \u003cp\u003eQuestions and Problems 277\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 Sequential Logic Design Using Verilog 281\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 Basics 281\u003c\/p\u003e \u003cp\u003e12.2 Examples Illustrating Non-blocking and Blocking Assignments 283\u003c\/p\u003e \u003cp\u003e12.3 RTL (Register Transfer Level) modeling 289\u003c\/p\u003e \u003cp\u003eQuestions and Problems 298\u003c\/p\u003e \u003cp\u003e\u003cb\u003e13 Implementation of Digital Design Using FPGA 301\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e13.1 Basics of FPGA 301\u003c\/p\u003e \u003cp\u003e13.1.1 LUTs (Look-Up Tables) 302\u003c\/p\u003e \u003cp\u003e13.1.2 Programmable Switch Matrix 308\u003c\/p\u003e \u003cp\u003e13.1.3 Configurable Logic Blocks (CLBs) 308\u003c\/p\u003e \u003cp\u003e13.1.4 FPGA Architecture 311\u003c\/p\u003e \u003cp\u003e13.1.5 FPGA Programming 311\u003c\/p\u003e \u003cp\u003e13.2 A Typical FPGA Chip 312\u003c\/p\u003e \u003cp\u003e13.2.1 Configuration Pins 314\u003c\/p\u003e \u003cp\u003e13.2.2 User I\/O Pins 315\u003c\/p\u003e \u003cp\u003e13.2.3 Power\/Ground Pins 315\u003c\/p\u003e \u003cp\u003e13.3 A Typical FPGA Board 315\u003c\/p\u003e \u003cp\u003e13.4 FPGA-based Design and Implementation 320\u003c\/p\u003e \u003cp\u003e13.4.1 Design 320\u003c\/p\u003e \u003cp\u003e13.4.2 Synthesis 320\u003c\/p\u003e \u003cp\u003e13.4.3 Implementation, Programming, and Verification 320\u003c\/p\u003e \u003cp\u003e13.5 FPGA Examples 322\u003c\/p\u003e \u003cp\u003eQuestions and Problems 374\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix A: Answers to Selected Problems 379\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix B: Glossary 389\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix C: Step-By-Step Tutorial for Downloading and Installing Xilinx Vivado IDE 395\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix D: Step-By-Step Tutorial for Creating \u0026amp; Simulating a Verilog Design Using Xilinx Vivado IDE 399 \u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eI Combinational Circuit 399\u003c\/p\u003e \u003cp\u003eII Sequential Circuit 407\u003c\/p\u003e \u003cp\u003e\u003cb\u003eAppendix E: Step-By-Step Procedure for Implementing FPGA-Based Design Using Vivado IDE \u0026amp; Nexys A7 FPGA Board 419 \u003c\/b\u003e\u003c\/p\u003e \u003cp\u003eI Combinational Circuit 419\u003c\/p\u003e \u003cp\u003eII FPGA Implementation of Sequential Circuit 426\u003c\/p\u003e \u003cp\u003eBibliography 437\u003c\/p\u003e \u003cp\u003eIndex 439\u003c\/p\u003e \u003cp\u003e\u003cb\u003eM. RAFIQUZZAMAN, PhD,\u003c\/b\u003e PE, is Professor of Electrical and Computer Engineering at California State Polytechnic University, Pomona. Dr. Rafiquzzaman has over 40 years of academic and industrial experiences. He is the founder and President of Rafi Systems, Inc., a manufacturer of biomedical devices (Intraocular lenses) in California. Dr. Rafiquzzaman authored several books on digital logic, microcontrollers, and microprocessors. His first book on microprocessors was published by Wiley in 1982.\u003c\/p\u003e","brand":"Wiley","offers":[{"title":"Default Title","offer_id":47989066662117,"sku":"NP9781119621638","price":104.0,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9781119621638.jpg?v=1761782656","url":"https:\/\/k12savings.com\/es\/products\/digital-logic-isbn-9781119621638","provider":"K12savings","version":"1.0","type":"link"}