{"product_id":"design-through-verilog-hdl-isbn-9780471441489","title":"Design Through Verilog HDL","description":"A comprehensive resource on Verilog HDL for beginners and experts  \u003cp\u003eLarge and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.\u003c\/p\u003e \u003cp\u003eDescribing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant.\u003c\/p\u003e \u003cp\u003eOther important topics covered include:\u003c\/p\u003e \u003cul\u003e \u003cli\u003ePrimitives\u003c\/li\u003e \u003cli\u003eGate and Net delays\u003c\/li\u003e \u003cli\u003eBuffers\u003c\/li\u003e \u003cli\u003eCMOS switches\u003c\/li\u003e \u003cli\u003eState machine design\u003c\/li\u003e \u003c\/ul\u003e Further, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book's final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.  \u003cp\u003eEach chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.\u003c\/p\u003e  PREFACE.  \u003cp\u003eACKNOWLEDGEMENTS.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e1 INTRODUCTION TO VLSI DESIGN.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e1.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e1.2 CONVENTIONAL APPROACH TO DIGITAL DESIGN.\u003c\/p\u003e \u003cp\u003e1.3 VLSI DESIGN.\u003c\/p\u003e \u003cp\u003e1.4 ASIC DESIGN FLOW.\u003c\/p\u003e \u003cp\u003e1.5 ROLE OF HDL.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e2 INTRODUCTION TO VERILOG.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e2.1 VERILOG AS AN HDL.\u003c\/p\u003e \u003cp\u003e2.2 LEVELS OF DESIGN DESCRIPTION.\u003c\/p\u003e \u003cp\u003e2.3 CONCURRENCY.\u003c\/p\u003e \u003cp\u003e2.4 SIMULATION AND SYNTHESIS.\u003c\/p\u003e \u003cp\u003e2.5 FUNCTIONAL VERIFICATION.\u003c\/p\u003e \u003cp\u003e2.6 SYSTEM TASKS.\u003c\/p\u003e \u003cp\u003e2.7 PROGRAMMING LANGUAGE INTERFACE (PLI).\u003c\/p\u003e \u003cp\u003e2.8 MODULE.\u003c\/p\u003e \u003cp\u003e2.9 SIMULATION AND SYNTHESIS TOOLS.\u003c\/p\u003e \u003cp\u003e2.10 TEST BENCHES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e3 LANGUAGE CONSTRUCTS AND CONVENTIONS IN VERILOG.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e3.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e3.2 KEYWORDS.\u003c\/p\u003e \u003cp\u003e3.3 IDENTIFIERS.\u003c\/p\u003e \u003cp\u003e3.4 WHITE SPACE CHARACTERS.\u003c\/p\u003e \u003cp\u003e3.5 COMMENTS.\u003c\/p\u003e \u003cp\u003e3.6 NUMBERS.\u003c\/p\u003e \u003cp\u003e3.7 STRINGS.\u003c\/p\u003e \u003cp\u003e3.8 LOGIC VALUES.\u003c\/p\u003e \u003cp\u003e3.9 STRENGTHS.\u003c\/p\u003e \u003cp\u003e3.10 DATA TYPES.\u003c\/p\u003e \u003cp\u003e3.11 SCALARS AND VECTORS.\u003c\/p\u003e \u003cp\u003e3.12 PARAMETERS.\u003c\/p\u003e \u003cp\u003e3.13 MEMORY.\u003c\/p\u003e \u003cp\u003e3.14 OPERATORS.\u003c\/p\u003e \u003cp\u003e3.15 SYSTEM TASKS.\u003c\/p\u003e \u003cp\u003e3.16 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e4 GATE LEVEL MODELING – 1.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e4.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e4.2 AND GATE PRIMITIVE.\u003c\/p\u003e \u003cp\u003e4.3 MODULE STRUCTURE.\u003c\/p\u003e \u003cp\u003e4.4 OTHER GATE PRIMITIVES.\u003c\/p\u003e \u003cp\u003e4.5 ILLUSTRATIVE EXAMPLES.\u003c\/p\u003e \u003cp\u003e4.6 TRI-STATE GATES.\u003c\/p\u003e \u003cp\u003e4.7 ARRAY OF INSTANCES OF PRIMITIVES.\u003c\/p\u003e \u003cp\u003e4.8 ADDITIONAL EXAMPLES.\u003c\/p\u003e \u003cp\u003e4.9 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e5 GATE LEVEL MODELING – 2.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e5.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e5.2 DESIGN OF FLIP-FLOPS WITH GATE PRIMITIVES.\u003c\/p\u003e \u003cp\u003e5.3 DELAYS.\u003c\/p\u003e \u003cp\u003e5.4 STRENGTHS AND CONTENTION RESOLUTION.\u003c\/p\u003e \u003cp\u003e5.5 NET TYPES.\u003c\/p\u003e \u003cp\u003e5.6 DESIGN OF BASIC CIRCUITS.\u003c\/p\u003e \u003cp\u003e5.7 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e6 MODELING AT DATA FLOW LEVEL.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e6.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e6.2 CONTINUOUS ASSIGNMENT STRUCTURES.\u003c\/p\u003e \u003cp\u003e6.3 DELAYS AND CONTINUOUS ASSIGNMENTS.\u003c\/p\u003e \u003cp\u003e6.4 ASSIGNMENT TO VECTORS.\u003c\/p\u003e \u003cp\u003e6.5 OPERATORS.\u003c\/p\u003e \u003cp\u003e6.6 ADDITIONAL EXAMPLES.\u003c\/p\u003e \u003cp\u003e6.7 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e7 BEHAVIORAL MODELING — 1.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e7.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e7.2 OPERATIONS AND ASSIGNMENTS.0\u003c\/p\u003e \u003cp\u003e7.3 FUNCTIONAL BIFURCATION.1\u003c\/p\u003e \u003cp\u003e7.4 INITIAL CONSTRUCT.\u003c\/p\u003e \u003cp\u003e7.5 ALWAYS CONSTRUCT.\u003c\/p\u003e \u003cp\u003e7.6 EXAMPLES.\u003c\/p\u003e \u003cp\u003e7.7 ASSIGNMENTS WITH DELAYS.\u003c\/p\u003e \u003cp\u003e7.8 wait CONSTRUCT.\u003c\/p\u003e \u003cp\u003e7.9 MULTIPLE ALWAYS BLOCKS.\u003c\/p\u003e \u003cp\u003e7.10 DESIGNS AT BEHAVIORAL LEVEL.\u003c\/p\u003e \u003cp\u003e7.11 BLOCKING AND NONBLOCKING ASSIGNMENTS.\u003c\/p\u003e \u003cp\u003e7.12 THE case STATEMENT.\u003c\/p\u003e \u003cp\u003e7.13 SIMULATION FLOW.\u003c\/p\u003e \u003cp\u003e7.14 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e8 BEHAVIORAL MODELING II.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e8.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e8.2 if AND if–else CONSTRUCTS.\u003c\/p\u003e \u003cp\u003e8.3 assign–deassign CONSTRUCT.\u003c\/p\u003e \u003cp\u003e8.4 repeat CONSTRUCT.\u003c\/p\u003e \u003cp\u003e8.5 for LOOP.\u003c\/p\u003e \u003cp\u003e8.6 THE disable CONSTRUCT.\u003c\/p\u003e \u003cp\u003e8.7 while LOOP.\u003c\/p\u003e \u003cp\u003e8.8 forever LOOP.\u003c\/p\u003e \u003cp\u003e8.9 PARALLEL BLOCKS.\u003c\/p\u003e \u003cp\u003e8.10 force–release CONSTRUCT.\u003c\/p\u003e \u003cp\u003e8.11 EVENT.\u003c\/p\u003e \u003cp\u003e8.12 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e9 FUNCTIONS, TASKS, AND USER-DEFINED PRIMITIVES.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e9.1 INTRODUCTIUON.\u003c\/p\u003e \u003cp\u003e9.2 FUNCTION.\u003c\/p\u003e \u003cp\u003e9.3 TASKS.\u003c\/p\u003e \u003cp\u003e9.4 USER-DEFINED PRIMITIVES (UDP).2\u003c\/p\u003e \u003cp\u003e9.5 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e10 SWITCH LEVEL MODELING 305\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e10.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e10.2 BASIC TRANSISTOR SWITCHES.5\u003c\/p\u003e \u003cp\u003e10.3 CMOS SWITCH.\u003c\/p\u003e \u003cp\u003e10.4 BIDIRECTIONAL GATES.\u003c\/p\u003e \u003cp\u003e10.5 TIME DELAYS WITH SWITCH PRIMITIVES.\u003c\/p\u003e \u003cp\u003e10.6 INSTANTIATIONS WITH STRENGTHS AND DELAYS.\u003c\/p\u003e \u003cp\u003e10.7 STRENGTH CONTENTION WITH TRIREG NETS.\u003c\/p\u003e \u003cp\u003e10.8 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e11 SYSTEM TASKS, FUNCTIONS, AND COMPILER DIRECTIVES 339\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e11.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e11.2 PARAMETERS.9\u003c\/p\u003e \u003cp\u003e11.3 PATH DELAYS.\u003c\/p\u003e \u003cp\u003e11.4 MODULE PARAMETERS.\u003c\/p\u003e \u003cp\u003e11.5 SYSTEM TASKS AND FUNCTIONS.\u003c\/p\u003e \u003cp\u003e11.6 FILE-BASED TASKS AND FUNCTIONS.\u003c\/p\u003e \u003cp\u003e11.7 COMPILER DIRECTIVES.\u003c\/p\u003e \u003cp\u003e11.8 HIERARCHICAL ACCESS.\u003c\/p\u003e \u003cp\u003e11.9 GENERAL OBSERVATIONS.\u003c\/p\u003e \u003cp\u003e11.10 EXERCISES.\u003c\/p\u003e \u003cp\u003e\u003cb\u003e12 QUEUES, PLAS, AND FSMS.\u003c\/b\u003e\u003c\/p\u003e \u003cp\u003e12.1 INTRODUCTION.\u003c\/p\u003e \u003cp\u003e12.2 QUEUES.\u003c\/p\u003e \u003cp\u003e12.3 PROGRAMMABLE LOGIC DEVICES (PLDs).\u003c\/p\u003e \u003cp\u003e12.4 DESIGN OF FINITE STATE MACHINES.\u003c\/p\u003e \u003cp\u003e12.5 EXERCISES.\u003c\/p\u003e \u003cp\u003eAPPENDIX A (Keywords and Their Significance).\u003c\/p\u003e \u003cp\u003eAPPENDIX B (Truth Tables of Gates and Switches).\u003c\/p\u003e \u003cp\u003eREFERENCES.\u003c\/p\u003e \u003cp\u003eINDEX.\u003c\/p\u003e  \"…this book is surely welcome…due to its simple but efficient structure, the book can be used both in academia and in industry.\" (IEEE Circuits \u0026amp; Devices, July\/August 2006)  \u003cp\u003e“...ideally suited for teaching digital hardware design techniques using a low-level programming language...highly recommended...” (\u003ci\u003eChoice\u003c\/i\u003e, Vol. 41, No. 8, April 2004)\u003c\/p\u003e \u003cp\u003e\"…enables readers to master Verilog as an HDL for design...engages the readers at every stage through the variety and number of examples.\" (\u003ci\u003eIEEE Solid-State Circuits Society Newsletter\u003c\/i\u003e, January 2004)\u003c\/p\u003e  \u003cb\u003eT. R. PADMANABHAN\u003c\/b\u003e, PhD, is Dean-Engineering, Amrita Institute of Technology, Amrita Vishwa Vidyapeetham, (Amrita University), Ettimadai (PO), Coimbatore, India. He is a Senior Member of IEEE as well as a Fellow of both India’s IE and IETE.  \u003cp\u003e\u003cb\u003eB. BALA TRIPURA SUNDARI\u003c\/b\u003e is a Senior Lecturer in the ECE Department of the Amrita Institute of Technology. She is a senior faculty member in the microelectronics center at the institute. She is a member of India’s IETE and ISTE.\u003c\/p\u003e  \u003cb\u003eA comprehensive resource on Verilog HDL for beginners and experts\u003c\/b\u003e  \u003cp\u003eLarge and complicated digital circuits can be incorporated into hardware by using Verilog, a hardware description language (HDL). A designer aspiring to master this versatile language must first become familiar with its constructs, practice their use in real applications, and apply them in combinations in order to be successful. \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e affords novices the opportunity to perform all of these tasks, while also offering seasoned professionals a comprehensive resource on this dynamic tool.\u003c\/p\u003e \u003cp\u003eDescribing a design using Verilog is only half the story: writing test-benches, testing a design for all its desired functions, and how identifying and removing the faults remain significant challenges. \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e addresses each of these issues concisely and effectively. The authors discuss constructs through illustrative examples that are tested with popular simulation packages, ensuring the subject matter remains practically relevant. Other important topics covered include:\u003c\/p\u003e \u003cul\u003e \u003cli\u003ePrimitives\u003c\/li\u003e \u003cli\u003eGate and Net delays\u003c\/li\u003e \u003cli\u003eBuffers\u003c\/li\u003e \u003cli\u003eCMOS switches\u003c\/li\u003e \u003cli\u003eState machine design\u003c\/li\u003e \u003c\/ul\u003e \u003cp\u003eFurther, the authors focus on illuminating the differences between gate level, data flow, and behavioral styles of Verilog, a critical distinction for designers. The book?s final chapters deal with advanced topics such as timescales, parameters and related constructs, queues, and switch level design.\u003c\/p\u003e \u003cp\u003eEach chapter concludes with exercises that both ensure readers have mastered the present material and stimulate readers to explore avenues of their own choosing. Written and assembled in a paced, logical manner, \u003ci\u003eDesign Through Verilog HDL\u003c\/i\u003e provides professionals, graduate students, and advanced undergraduates with a one-of-a-kind resource.\u003c\/p\u003e","brand":"Wiley-IEEE Press","offers":[{"title":"Default Title","offer_id":47989047132389,"sku":"NP9780471441489","price":171.95,"currency_code":"USD","in_stock":false}],"thumbnail_url":"\/\/cdn.shopify.com\/s\/files\/1\/1842\/7735\/files\/9780471441489.jpg?v=1761782573","url":"https:\/\/k12savings.com\/es\/products\/design-through-verilog-hdl-isbn-9780471441489","provider":"K12savings","version":"1.0","type":"link"}