Built In Test for VLSI

This handbook provides ready access to all of the major concepts, techniques, problems, and solutions in the emerging field of pseudorandom pattern testing. Until now, the literature in this area has been widely scattered, and published work, written by professionals in several disciplines, has treated notation and mathematics in ways that vary from source to source. This book opens with a clear description of the shortcomings of conventional testing as applied to complex digital circuits, revewing by comparison the principles of design for testability of more advanced digital technology. Offers in-depth discussions of test sequence generation and response data compression, including pseudorandom sequence generators; the mathematics of shift-register sequences and their potential for built-in testing. Also details random and memory testing and the problems of assessing the efficiency of such tests, and the limitations and practical concerns of built-in testing. Digital Testing and the Need for Testable Design.

Principles of Testable Design.

Pseudorandom Sequence Generators.

Test Response Compression Techniques.

Shift-Register Polynomial Division.

Special-Purpose Shift-Register Circuits.

Random Pattern Built-In Test.

Built-In Test Structures.

Limitations and Other Concerns of Random Pattern Testing.

Test System Requirements for Built-In Test.

Appendix.

References.

Index.

Paul H. Bardell and W. H. McAnney are the authors of Built In Test for VLSI: Pseudorandom Techniques, published by Wiley.